1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
25 #define CONFIG_SYS_UNIFY_CACHE
28 # define CONFIG_MII_INIT 1
29 # define CONFIG_SYS_DISCOVER_PHY
30 # define CONFIG_SYS_RX_ETH_BUFFER 8
31 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
32 # ifndef CONFIG_SYS_DISCOVER_PHY
33 # define FECDUPLEX FULL
34 # define FECSPEED _100BASET
35 # endif /* CONFIG_SYS_DISCOVER_PHY */
47 # define CONFIG_IPADDR 192.162.1.2
48 # define CONFIG_NETMASK 255.255.255.0
49 # define CONFIG_SERVERIP 192.162.1.1
50 # define CONFIG_GATEWAYIP 192.162.1.1
53 #define CONFIG_HOSTNAME "M5329EVB"
54 #define CONFIG_EXTRA_ENV_SETTINGS \
56 "loadaddr=40010000\0" \
57 "u-boot=u-boot.bin\0" \
58 "load=tftp ${loadaddr) ${u-boot}\0" \
59 "upd=run load; run prog\0" \
60 "prog=prot off 0 3ffff;" \
62 "cp.b ${loadaddr} 0 ${filesize};" \
66 #define CONFIG_PRAM 512 /* 512 KB */
68 #define CONFIG_SYS_CLK 80000000
69 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
71 #define CONFIG_SYS_MBAR 0xFC000000
73 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
76 * Low Level Configuration Settings
77 * (address mappings, register initial values, etc.)
78 * You should know what you are doing if you make changes here.
80 /*-----------------------------------------------------------------------
81 * Definitions for initial stack pointer and data area (in DPRAM)
83 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
84 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
85 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
86 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
87 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
89 /*-----------------------------------------------------------------------
90 * Start addresses for the final memory configuration
91 * (Set up by the startup code)
92 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
94 #define CONFIG_SYS_SDRAM_BASE 0x40000000
95 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
96 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
97 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
98 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
99 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
100 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
102 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
103 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
105 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
108 * For booting Linux, the board info and command line data
109 * have to be in the first 8 MB of memory, since this is
110 * the maximum mapped by the Linux kernel during initialization ??
112 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
113 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
115 /*-----------------------------------------------------------------------
118 #ifdef CONFIG_SYS_FLASH_CFI
119 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
120 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
121 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
124 #ifdef CONFIG_NANDFLASH_SIZE
125 # define CONFIG_SYS_MAX_NAND_DEVICE 1
126 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
127 # define CONFIG_SYS_NAND_SIZE 1
128 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
129 # define NAND_ALLOW_ERASE_ALL 1
132 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
134 /* Configuration for environment
135 * Environment is embedded in u-boot in the second sector of the flash
138 #define LDS_BOARD_TEXT \
139 . = DEFINED(env_offset) ? env_offset : .; \
140 env/embedded.o(.text*);
142 /*-----------------------------------------------------------------------
143 * Cache Configuration
146 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
147 CONFIG_SYS_INIT_RAM_SIZE - 8)
148 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
149 CONFIG_SYS_INIT_RAM_SIZE - 4)
150 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
151 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
152 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
153 CF_ACR_EN | CF_ACR_SM_ALL)
154 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
157 /*-----------------------------------------------------------------------
158 * Chipselect bank definitions
161 * CS0 - NOR Flash 1, 2, 4, or 8MB
162 * CS1 - CompactFlash and registers
163 * CS2 - NAND Flash 16, 32, or 64MB
168 #define CONFIG_SYS_CS0_BASE 0
169 #define CONFIG_SYS_CS0_MASK 0x007f0001
170 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
172 #define CONFIG_SYS_CS1_BASE 0x10000000
173 #define CONFIG_SYS_CS1_MASK 0x001f0001
174 #define CONFIG_SYS_CS1_CTRL 0x002A3780
176 #ifdef CONFIG_NANDFLASH_SIZE
177 #define CONFIG_SYS_CS2_BASE 0x20000000
178 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
179 #define CONFIG_SYS_CS2_CTRL 0x00001f60
182 #endif /* _M5329EVB_H */