1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
25 #define CONFIG_SYS_UNIFY_CACHE
28 # define CONFIG_SYS_DISCOVER_PHY
29 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
30 # ifndef CONFIG_SYS_DISCOVER_PHY
31 # define FECDUPLEX FULL
32 # define FECSPEED _100BASET
33 # endif /* CONFIG_SYS_DISCOVER_PHY */
39 # define CONFIG_IPADDR 192.162.1.2
40 # define CONFIG_NETMASK 255.255.255.0
41 # define CONFIG_SERVERIP 192.162.1.1
42 # define CONFIG_GATEWAYIP 192.162.1.1
45 #define CONFIG_HOSTNAME "M5329EVB"
46 #define CONFIG_EXTRA_ENV_SETTINGS \
48 "loadaddr=40010000\0" \
49 "u-boot=u-boot.bin\0" \
50 "load=tftp ${loadaddr) ${u-boot}\0" \
51 "upd=run load; run prog\0" \
52 "prog=prot off 0 3ffff;" \
54 "cp.b ${loadaddr} 0 ${filesize};" \
58 #define CONFIG_PRAM 512 /* 512 KB */
60 #define CONFIG_SYS_CLK 80000000
61 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
63 #define CONFIG_SYS_MBAR 0xFC000000
65 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
68 * Low Level Configuration Settings
69 * (address mappings, register initial values, etc.)
70 * You should know what you are doing if you make changes here.
72 /*-----------------------------------------------------------------------
73 * Definitions for initial stack pointer and data area (in DPRAM)
75 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
76 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
77 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
78 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
79 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
81 /*-----------------------------------------------------------------------
82 * Start addresses for the final memory configuration
83 * (Set up by the startup code)
84 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
86 #define CONFIG_SYS_SDRAM_BASE 0x40000000
87 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
88 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
89 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
90 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
91 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
92 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
94 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
96 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
99 * For booting Linux, the board info and command line data
100 * have to be in the first 8 MB of memory, since this is
101 * the maximum mapped by the Linux kernel during initialization ??
103 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
104 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
106 /*-----------------------------------------------------------------------
109 #ifdef CONFIG_SYS_FLASH_CFI
110 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
111 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
112 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
115 #ifdef CONFIG_CMD_NAND
116 # define CONFIG_SYS_MAX_NAND_DEVICE 1
117 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
118 # define CONFIG_SYS_NAND_SIZE 1
119 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
120 # define NAND_ALLOW_ERASE_ALL 1
123 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
125 /* Configuration for environment
126 * Environment is embedded in u-boot in the second sector of the flash
129 #define LDS_BOARD_TEXT \
130 . = DEFINED(env_offset) ? env_offset : .; \
131 env/embedded.o(.text*);
133 /*-----------------------------------------------------------------------
134 * Cache Configuration
137 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
138 CONFIG_SYS_INIT_RAM_SIZE - 8)
139 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
140 CONFIG_SYS_INIT_RAM_SIZE - 4)
141 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
142 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
143 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
144 CF_ACR_EN | CF_ACR_SM_ALL)
145 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
148 /*-----------------------------------------------------------------------
149 * Chipselect bank definitions
152 * CS0 - NOR Flash 1, 2, 4, or 8MB
153 * CS1 - CompactFlash and registers
154 * CS2 - NAND Flash 16, 32, or 64MB
159 #define CONFIG_SYS_CS0_BASE 0
160 #define CONFIG_SYS_CS0_MASK 0x007f0001
161 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
163 #define CONFIG_SYS_CS1_BASE 0x10000000
164 #define CONFIG_SYS_CS1_MASK 0x001f0001
165 #define CONFIG_SYS_CS1_CTRL 0x002A3780
167 #ifdef CONFIG_CMD_NAND
168 #define CONFIG_SYS_CS2_BASE 0x20000000
169 #define CONFIG_SYS_CS2_MASK (16 << 20)
170 #define CONFIG_SYS_CS2_CTRL 0x00001f60
173 #endif /* _M5329EVB_H */