include/configs/M5329EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5329 FireEngine board.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5329EVB_H
  14 #define _M5329EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  24
  25 #define CONFIG_SYS_UNIFY_CACHE
  26
  27 #ifdef CONFIG_MCFFEC
  28 #       define CONFIG_SYS_DISCOVER_PHY
  29 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  30 #       ifndef CONFIG_SYS_DISCOVER_PHY
  31 #               define FECDUPLEX        FULL
  32 #               define FECSPEED         _100BASET
  33 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  34 #endif
  35
  36 #define CONFIG_MCFRTC
  37 #undef RTC_DEBUG
  38
  39 /* Timer */
  40 #define CONFIG_MCFTMR
  41
  42 /* I2C */
  43
  44 #ifdef CONFIG_MCFFEC
  45 #       define CONFIG_IPADDR    192.162.1.2
  46 #       define CONFIG_NETMASK   255.255.255.0
  47 #       define CONFIG_SERVERIP  192.162.1.1
  48 #       define CONFIG_GATEWAYIP 192.162.1.1
  49 #endif                          /* FEC_ENET */
  50
  51 #define CONFIG_HOSTNAME         "M5329EVB"
  52 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  53         "netdev=eth0\0"                 \
  54         "loadaddr=40010000\0"   \
  55         "u-boot=u-boot.bin\0"   \
  56         "load=tftp ${loadaddr) ${u-boot}\0"     \
  57         "upd=run load; run prog\0"      \
  58         "prog=prot off 0 3ffff;"        \
  59         "era 0 3ffff;"  \
  60         "cp.b ${loadaddr} 0 ${filesize};"       \
  61         "save\0"        \
  62         ""
  63
  64 #define CONFIG_PRAM             512     /* 512 KB */
  65
  66 #define CONFIG_SYS_CLK                  80000000
  67 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 3
  68
  69 #define CONFIG_SYS_MBAR         0xFC000000
  70
  71 #define CONFIG_SYS_LATCH_ADDR           (CONFIG_SYS_CS1_BASE + 0x80000)
  72
  73 /*
  74  * Low Level Configuration Settings
  75  * (address mappings, register initial values, etc.)
  76  * You should know what you are doing if you make changes here.
  77  */
  78 /*-----------------------------------------------------------------------
  79  * Definitions for initial stack pointer and data area (in DPRAM)
  80  */
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
  83 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  84 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  85 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  86
  87 /*-----------------------------------------------------------------------
  88  * Start addresses for the final memory configuration
  89  * (Set up by the startup code)
  90  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  91  */
  92 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  93 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
  94 #define CONFIG_SYS_SDRAM_CFG1           0x53722730
  95 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  96 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
  97 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
  98 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
  99
 100 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 101 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 102
 103 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 104
 105 /*
 106  * For booting Linux, the board info and command line data
 107  * have to be in the first 8 MB of memory, since this is
 108  * the maximum mapped by the Linux kernel during initialization ??
 109  */
 110 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 111 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 112
 113 /*-----------------------------------------------------------------------
 114  * FLASH organization
 115  */
 116 #ifdef CONFIG_SYS_FLASH_CFI
 117 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 118 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 119 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 120 #endif
 121
 122 #ifdef CONFIG_NANDFLASH_SIZE
 123 #       define CONFIG_SYS_MAX_NAND_DEVICE       1
 124 #       define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 125 #       define CONFIG_SYS_NAND_SIZE             1
 126 #       define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
 127 #       define NAND_ALLOW_ERASE_ALL     1
 128 #endif
 129
 130 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 131
 132 /* Configuration for environment
 133  * Environment is embedded in u-boot in the second sector of the flash
 134  */
 135
 136 #define LDS_BOARD_TEXT \
 137         . = DEFINED(env_offset) ? env_offset : .; \
 138         env/embedded.o(.text*);
 139
 140 /*-----------------------------------------------------------------------
 141  * Cache Configuration
 142  */
 143
 144 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 145                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 146 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 147                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 148 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 149 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 150                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 151                                          CF_ACR_EN | CF_ACR_SM_ALL)
 152 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 153                                          CF_CACR_DCM_P)
 154
 155 /*-----------------------------------------------------------------------
 156  * Chipselect bank definitions
 157  */
 158 /*
 159  * CS0 - NOR Flash 1, 2, 4, or 8MB
 160  * CS1 - CompactFlash and registers
 161  * CS2 - NAND Flash 16, 32, or 64MB
 162  * CS3 - Available
 163  * CS4 - Available
 164  * CS5 - Available
 165  */
 166 #define CONFIG_SYS_CS0_BASE             0
 167 #define CONFIG_SYS_CS0_MASK             0x007f0001
 168 #define CONFIG_SYS_CS0_CTRL             0x00001fa0
 169
 170 #define CONFIG_SYS_CS1_BASE             0x10000000
 171 #define CONFIG_SYS_CS1_MASK             0x001f0001
 172 #define CONFIG_SYS_CS1_CTRL             0x002A3780
 173
 174 #ifdef CONFIG_NANDFLASH_SIZE
 175 #define CONFIG_SYS_CS2_BASE             0x20000000
 176 #define CONFIG_SYS_CS2_MASK             ((CONFIG_NANDFLASH_SIZE << 20) | 1)
 177 #define CONFIG_SYS_CS2_CTRL             0x00001f60
 178 #endif
 179
 180 #endif                          /* _M5329EVB_H */