1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
25 #define CONFIG_SYS_UNIFY_CACHE
28 # define CONFIG_MII_INIT 1
29 # define CONFIG_SYS_DISCOVER_PHY
30 # define CONFIG_SYS_RX_ETH_BUFFER 8
31 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
32 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
33 # ifndef CONFIG_SYS_DISCOVER_PHY
34 # define FECDUPLEX FULL
35 # define FECSPEED _100BASET
37 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
38 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
40 # endif /* CONFIG_SYS_DISCOVER_PHY */
52 # define CONFIG_IPADDR 192.162.1.2
53 # define CONFIG_NETMASK 255.255.255.0
54 # define CONFIG_SERVERIP 192.162.1.1
55 # define CONFIG_GATEWAYIP 192.162.1.1
58 #define CONFIG_HOSTNAME "M5329EVB"
59 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "loadaddr=40010000\0" \
62 "u-boot=u-boot.bin\0" \
63 "load=tftp ${loadaddr) ${u-boot}\0" \
64 "upd=run load; run prog\0" \
65 "prog=prot off 0 3ffff;" \
67 "cp.b ${loadaddr} 0 ${filesize};" \
71 #define CONFIG_PRAM 512 /* 512 KB */
73 #define CONFIG_SYS_CLK 80000000
74 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
76 #define CONFIG_SYS_MBAR 0xFC000000
78 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
81 * Low Level Configuration Settings
82 * (address mappings, register initial values, etc.)
83 * You should know what you are doing if you make changes here.
85 /*-----------------------------------------------------------------------
86 * Definitions for initial stack pointer and data area (in DPRAM)
88 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
89 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
90 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
91 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
92 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
94 /*-----------------------------------------------------------------------
95 * Start addresses for the final memory configuration
96 * (Set up by the startup code)
97 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
99 #define CONFIG_SYS_SDRAM_BASE 0x40000000
100 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
101 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
102 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
103 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
104 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
105 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
107 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
108 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
110 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
113 * For booting Linux, the board info and command line data
114 * have to be in the first 8 MB of memory, since this is
115 * the maximum mapped by the Linux kernel during initialization ??
117 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
118 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
120 /*-----------------------------------------------------------------------
123 #ifdef CONFIG_SYS_FLASH_CFI
124 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
125 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
126 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
129 #ifdef CONFIG_NANDFLASH_SIZE
130 # define CONFIG_SYS_MAX_NAND_DEVICE 1
131 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
132 # define CONFIG_SYS_NAND_SIZE 1
133 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
134 # define NAND_ALLOW_ERASE_ALL 1
137 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
139 /* Configuration for environment
140 * Environment is embedded in u-boot in the second sector of the flash
143 #define LDS_BOARD_TEXT \
144 . = DEFINED(env_offset) ? env_offset : .; \
145 env/embedded.o(.text*);
147 /*-----------------------------------------------------------------------
148 * Cache Configuration
151 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
152 CONFIG_SYS_INIT_RAM_SIZE - 8)
153 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
154 CONFIG_SYS_INIT_RAM_SIZE - 4)
155 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
156 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
157 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
158 CF_ACR_EN | CF_ACR_SM_ALL)
159 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
162 /*-----------------------------------------------------------------------
163 * Chipselect bank definitions
166 * CS0 - NOR Flash 1, 2, 4, or 8MB
167 * CS1 - CompactFlash and registers
168 * CS2 - NAND Flash 16, 32, or 64MB
173 #define CONFIG_SYS_CS0_BASE 0
174 #define CONFIG_SYS_CS0_MASK 0x007f0001
175 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
177 #define CONFIG_SYS_CS1_BASE 0x10000000
178 #define CONFIG_SYS_CS1_MASK 0x001f0001
179 #define CONFIG_SYS_CS1_CTRL 0x002A3780
181 #ifdef CONFIG_NANDFLASH_SIZE
182 #define CONFIG_SYS_CS2_BASE 0x20000000
183 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
184 #define CONFIG_SYS_CS2_CTRL 0x00001f60
187 #endif /* _M5329EVB_H */