include/configs/M53017EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF53017EVB.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M53017EVB_H
  14 #define _M53017EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_MCFUART
  22 #define CONFIG_SYS_UART_PORT            (0)
  23
  24 #undef CONFIG_WATCHDOG
  25 #define CONFIG_WATCHDOG_TIMEOUT         5000
  26
  27 #define CONFIG_SYS_UNIFY_CACHE
  28
  29 #ifdef CONFIG_MCFFEC
  30 #       define CONFIG_MII_INIT          1
  31 #       define CONFIG_SYS_DISCOVER_PHY
  32 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  33 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  34 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  35 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36 #       define CONFIG_HAS_ETH1
  37
  38 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  39 #       ifndef CONFIG_SYS_DISCOVER_PHY
  40 #               define FECDUPLEX        FULL
  41 #               define FECSPEED         _100BASET
  42 #       else
  43 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45 #               endif
  46 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  47 #endif
  48
  49 #define CONFIG_MCFRTC
  50 #undef RTC_DEBUG
  51 #define CONFIG_SYS_RTC_CNT              (0x8000)
  52 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  53
  54 /* Timer */
  55 #define CONFIG_MCFTMR
  56
  57 /* I2C */
  58 #define CONFIG_SYS_I2C_FSL
  59 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  60 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  61 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  62 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  63
  64 #define CONFIG_UDP_CHECKSUM
  65
  66 #ifdef CONFIG_MCFFEC
  67 #       define CONFIG_IPADDR    192.162.1.2
  68 #       define CONFIG_NETMASK   255.255.255.0
  69 #       define CONFIG_SERVERIP  192.162.1.1
  70 #       define CONFIG_GATEWAYIP 192.162.1.1
  71 #endif                          /* FEC_ENET */
  72
  73 #define CONFIG_HOSTNAME         "M53017"
  74 #define CONFIG_EXTRA_ENV_SETTINGS               \
  75         "netdev=eth0\0"                         \
  76         "loadaddr=40010000\0"                   \
  77         "u-boot=u-boot.bin\0"                   \
  78         "load=tftp ${loadaddr) ${u-boot}\0"     \
  79         "upd=run load; run prog\0"              \
  80         "prog=prot off 0 3ffff;"                \
  81         "era 0 3ffff;"                          \
  82         "cp.b ${loadaddr} 0 ${filesize};"       \
  83         "save\0"                                \
  84         ""
  85
  86 #define CONFIG_PRAM             512     /* 512 KB */
  87
  88 #define CONFIG_SYS_LOAD_ADDR    0x40010000
  89
  90 #define CONFIG_SYS_CLK          80000000
  91 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
  92
  93 #define CONFIG_SYS_MBAR         0xFC000000
  94
  95 /*
  96  * Low Level Configuration Settings
  97  * (address mappings, register initial values, etc.)
  98  * You should know what you are doing if you make changes here.
  99  */
 100 /*
 101  * Definitions for initial stack pointer and data area (in DPRAM)
 102  */
 103 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 104 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 105 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 106 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 107 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 108
 109 /*
 110  * Start addresses for the final memory configuration
 111  * (Set up by the startup code)
 112  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 113  */
 114 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 115 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 116 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 117 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 118 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 119 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 120 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 121
 122 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 123 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 124
 125 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 126 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 127
 128 /*
 129  * For booting Linux, the board info and command line data
 130  * have to be in the first 8 MB of memory, since this is
 131  * the maximum mapped by the Linux kernel during initialization ??
 132  */
 133 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 134 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 135
 136 /*-----------------------------------------------------------------------
 137  * FLASH organization
 138  */
 139 #ifdef CONFIG_SYS_FLASH_CFI
 140 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 141 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 142 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 143 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 144 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 145 #endif
 146
 147 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 148
 149 /* Configuration for environment
 150  * Environment is embedded in u-boot in the second sector of the flash
 151  */
 152
 153 #define LDS_BOARD_TEXT \
 154         . = DEFINED(env_offset) ? env_offset : .; \
 155         env/embedded.o(.text*)
 156
 157 /*-----------------------------------------------------------------------
 158  * Cache Configuration
 159  */
 160 #define CONFIG_SYS_CACHELINE_SIZE       16
 161
 162 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 163                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 164 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 165                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 166 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 167 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 168                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 169                                          CF_ACR_EN | CF_ACR_SM_ALL)
 170 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 171                                          CF_CACR_DCM_P)
 172
 173 /*-----------------------------------------------------------------------
 174  * Chipselect bank definitions
 175  */
 176 /*
 177  * CS0 - NOR Flash
 178  * CS1 - Ext SRAM
 179  * CS2 - Available
 180  * CS3 - Available
 181  * CS4 - Available
 182  * CS5 - Available
 183  */
 184 #define CONFIG_SYS_CS0_BASE             0
 185 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 186 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 187
 188 #define CONFIG_SYS_CS1_BASE             0xC0000000
 189 #define CONFIG_SYS_CS1_MASK             0x00070001
 190 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 191
 192 #endif                          /* _M53017EVB_H */