1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF53017EVB.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CFG_SYS_UART_PORT (0)
24 # define CFG_SYS_TX_ETH_BUFFER 8
25 # define CFG_SYS_FEC_BUF_USE_SRAM
28 #define CFG_SYS_RTC_CNT (0x8000)
29 #define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
34 # define CONFIG_IPADDR 192.162.1.2
35 # define CONFIG_NETMASK 255.255.255.0
36 # define CONFIG_SERVERIP 192.162.1.1
37 # define CONFIG_GATEWAYIP 192.162.1.1
40 #define CONFIG_HOSTNAME "M53017"
41 #define CONFIG_EXTRA_ENV_SETTINGS \
43 "loadaddr=40010000\0" \
44 "u-boot=u-boot.bin\0" \
45 "load=tftp ${loadaddr) ${u-boot}\0" \
46 "upd=run load; run prog\0" \
47 "prog=prot off 0 3ffff;" \
49 "cp.b ${loadaddr} 0 ${filesize};" \
53 #define CONFIG_PRAM 512 /* 512 KB */
55 #define CFG_SYS_CLK 80000000
56 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
58 #define CFG_SYS_MBAR 0xFC000000
61 * Low Level Configuration Settings
62 * (address mappings, register initial values, etc.)
63 * You should know what you are doing if you make changes here.
66 * Definitions for initial stack pointer and data area (in DPRAM)
68 #define CFG_SYS_INIT_RAM_ADDR 0x80000000
69 #define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
70 #define CFG_SYS_INIT_RAM_CTRL 0x221
73 * Start addresses for the final memory configuration
74 * (Set up by the startup code)
75 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
77 #define CFG_SYS_SDRAM_BASE 0x40000000
78 #define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
79 #define CFG_SYS_SDRAM_CFG1 0x43711630
80 #define CFG_SYS_SDRAM_CFG2 0x56670000
81 #define CFG_SYS_SDRAM_CTRL 0xE1092000
82 #define CFG_SYS_SDRAM_EMOD 0x80010000
83 #define CFG_SYS_SDRAM_MODE 0x00CD0000
86 * For booting Linux, the board info and command line data
87 * have to be in the first 8 MB of memory, since this is
88 * the maximum mapped by the Linux kernel during initialization ??
90 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
92 /*-----------------------------------------------------------------------
95 #ifdef CONFIG_SYS_FLASH_CFI
96 # define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
99 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
101 /* Configuration for environment
102 * Environment is embedded in u-boot in the second sector of the flash
105 #define LDS_BOARD_TEXT \
106 . = DEFINED(env_offset) ? env_offset : .; \
107 env/embedded.o(.text*)
109 /*-----------------------------------------------------------------------
110 * Cache Configuration
113 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
114 CFG_SYS_INIT_RAM_SIZE - 8)
115 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
116 CFG_SYS_INIT_RAM_SIZE - 4)
117 #define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
118 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
119 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
120 CF_ACR_EN | CF_ACR_SM_ALL)
121 #define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
124 /*-----------------------------------------------------------------------
125 * Chipselect bank definitions
135 #define CFG_SYS_CS0_BASE 0
136 #define CFG_SYS_CS0_MASK 0x00FF0001
137 #define CFG_SYS_CS0_CTRL 0x00001FA0
139 #define CFG_SYS_CS1_BASE 0xC0000000
140 #define CFG_SYS_CS1_MASK 0x00070001
141 #define CFG_SYS_CS1_CTRL 0x00001FA0
143 #endif /* _M53017EVB_H */