include/configs/M53017EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF53017EVB.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M53017EVB_H
  14 #define _M53017EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #define CONFIG_WATCHDOG_TIMEOUT         5000
  24
  25 #define CONFIG_SYS_UNIFY_CACHE
  26
  27 #ifdef CONFIG_MCFFEC
  28 #       define CONFIG_MII_INIT          1
  29 #       define CONFIG_SYS_DISCOVER_PHY
  30 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  31 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  32 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  33
  34 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  35 #       ifndef CONFIG_SYS_DISCOVER_PHY
  36 #               define FECDUPLEX        FULL
  37 #               define FECSPEED         _100BASET
  38 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  39 #endif
  40
  41 #define CONFIG_MCFRTC
  42 #undef RTC_DEBUG
  43 #define CONFIG_SYS_RTC_CNT              (0x8000)
  44 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  45
  46 /* Timer */
  47 #define CONFIG_MCFTMR
  48
  49 /* I2C */
  50
  51 #ifdef CONFIG_MCFFEC
  52 #       define CONFIG_IPADDR    192.162.1.2
  53 #       define CONFIG_NETMASK   255.255.255.0
  54 #       define CONFIG_SERVERIP  192.162.1.1
  55 #       define CONFIG_GATEWAYIP 192.162.1.1
  56 #endif                          /* FEC_ENET */
  57
  58 #define CONFIG_HOSTNAME         "M53017"
  59 #define CONFIG_EXTRA_ENV_SETTINGS               \
  60         "netdev=eth0\0"                         \
  61         "loadaddr=40010000\0"                   \
  62         "u-boot=u-boot.bin\0"                   \
  63         "load=tftp ${loadaddr) ${u-boot}\0"     \
  64         "upd=run load; run prog\0"              \
  65         "prog=prot off 0 3ffff;"                \
  66         "era 0 3ffff;"                          \
  67         "cp.b ${loadaddr} 0 ${filesize};"       \
  68         "save\0"                                \
  69         ""
  70
  71 #define CONFIG_PRAM             512     /* 512 KB */
  72
  73 #define CONFIG_SYS_CLK          80000000
  74 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
  75
  76 #define CONFIG_SYS_MBAR         0xFC000000
  77
  78 /*
  79  * Low Level Configuration Settings
  80  * (address mappings, register initial values, etc.)
  81  * You should know what you are doing if you make changes here.
  82  */
  83 /*
  84  * Definitions for initial stack pointer and data area (in DPRAM)
  85  */
  86 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  87 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
  88 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  89 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  90 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  91
  92 /*
  93  * Start addresses for the final memory configuration
  94  * (Set up by the startup code)
  95  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  96  */
  97 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  98 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
  99 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 100 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 101 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 102 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 103 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 104
 105 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 106 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 107
 108 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 109
 110 /*
 111  * For booting Linux, the board info and command line data
 112  * have to be in the first 8 MB of memory, since this is
 113  * the maximum mapped by the Linux kernel during initialization ??
 114  */
 115 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 116 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 117
 118 /*-----------------------------------------------------------------------
 119  * FLASH organization
 120  */
 121 #ifdef CONFIG_SYS_FLASH_CFI
 122 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 123 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 124 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 125 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 126 #endif
 127
 128 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 129
 130 /* Configuration for environment
 131  * Environment is embedded in u-boot in the second sector of the flash
 132  */
 133
 134 #define LDS_BOARD_TEXT \
 135         . = DEFINED(env_offset) ? env_offset : .; \
 136         env/embedded.o(.text*)
 137
 138 /*-----------------------------------------------------------------------
 139  * Cache Configuration
 140  */
 141
 142 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 143                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 144 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 145                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 146 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 147 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 148                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 149                                          CF_ACR_EN | CF_ACR_SM_ALL)
 150 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 151                                          CF_CACR_DCM_P)
 152
 153 /*-----------------------------------------------------------------------
 154  * Chipselect bank definitions
 155  */
 156 /*
 157  * CS0 - NOR Flash
 158  * CS1 - Ext SRAM
 159  * CS2 - Available
 160  * CS3 - Available
 161  * CS4 - Available
 162  * CS5 - Available
 163  */
 164 #define CONFIG_SYS_CS0_BASE             0
 165 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 166 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 167
 168 #define CONFIG_SYS_CS1_BASE             0xC0000000
 169 #define CONFIG_SYS_CS1_MASK             0x00070001
 170 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 171
 172 #endif                          /* _M53017EVB_H */