include/configs/M53017EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF53017EVB.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M53017EVB_H
  14 #define _M53017EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #define CONFIG_WATCHDOG_TIMEOUT         5000
  24
  25 #define CONFIG_SYS_UNIFY_CACHE
  26
  27 #ifdef CONFIG_MCFFEC
  28 #       define CONFIG_MII_INIT          1
  29 #       define CONFIG_SYS_DISCOVER_PHY
  30 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  31 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  32 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  33 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  34 #       define CONFIG_HAS_ETH1
  35
  36 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  37 #       ifndef CONFIG_SYS_DISCOVER_PHY
  38 #               define FECDUPLEX        FULL
  39 #               define FECSPEED         _100BASET
  40 #       else
  41 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  42 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  43 #               endif
  44 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  45 #endif
  46
  47 #define CONFIG_MCFRTC
  48 #undef RTC_DEBUG
  49 #define CONFIG_SYS_RTC_CNT              (0x8000)
  50 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  51
  52 /* Timer */
  53 #define CONFIG_MCFTMR
  54
  55 /* I2C */
  56
  57 #ifdef CONFIG_MCFFEC
  58 #       define CONFIG_IPADDR    192.162.1.2
  59 #       define CONFIG_NETMASK   255.255.255.0
  60 #       define CONFIG_SERVERIP  192.162.1.1
  61 #       define CONFIG_GATEWAYIP 192.162.1.1
  62 #endif                          /* FEC_ENET */
  63
  64 #define CONFIG_HOSTNAME         "M53017"
  65 #define CONFIG_EXTRA_ENV_SETTINGS               \
  66         "netdev=eth0\0"                         \
  67         "loadaddr=40010000\0"                   \
  68         "u-boot=u-boot.bin\0"                   \
  69         "load=tftp ${loadaddr) ${u-boot}\0"     \
  70         "upd=run load; run prog\0"              \
  71         "prog=prot off 0 3ffff;"                \
  72         "era 0 3ffff;"                          \
  73         "cp.b ${loadaddr} 0 ${filesize};"       \
  74         "save\0"                                \
  75         ""
  76
  77 #define CONFIG_PRAM             512     /* 512 KB */
  78
  79 #define CONFIG_SYS_CLK          80000000
  80 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
  81
  82 #define CONFIG_SYS_MBAR         0xFC000000
  83
  84 /*
  85  * Low Level Configuration Settings
  86  * (address mappings, register initial values, etc.)
  87  * You should know what you are doing if you make changes here.
  88  */
  89 /*
  90  * Definitions for initial stack pointer and data area (in DPRAM)
  91  */
  92 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  93 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
  94 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  95 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  96 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  97
  98 /*
  99  * Start addresses for the final memory configuration
 100  * (Set up by the startup code)
 101  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 102  */
 103 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 104 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 105 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 106 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 107 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 108 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 109 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 110
 111 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 112 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 113
 114 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 115
 116 /*
 117  * For booting Linux, the board info and command line data
 118  * have to be in the first 8 MB of memory, since this is
 119  * the maximum mapped by the Linux kernel during initialization ??
 120  */
 121 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 122 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 123
 124 /*-----------------------------------------------------------------------
 125  * FLASH organization
 126  */
 127 #ifdef CONFIG_SYS_FLASH_CFI
 128 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 129 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 130 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 131 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 132 #endif
 133
 134 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 135
 136 /* Configuration for environment
 137  * Environment is embedded in u-boot in the second sector of the flash
 138  */
 139
 140 #define LDS_BOARD_TEXT \
 141         . = DEFINED(env_offset) ? env_offset : .; \
 142         env/embedded.o(.text*)
 143
 144 /*-----------------------------------------------------------------------
 145  * Cache Configuration
 146  */
 147
 148 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 149                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 150 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 151                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 152 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 153 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 154                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 155                                          CF_ACR_EN | CF_ACR_SM_ALL)
 156 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 157                                          CF_CACR_DCM_P)
 158
 159 /*-----------------------------------------------------------------------
 160  * Chipselect bank definitions
 161  */
 162 /*
 163  * CS0 - NOR Flash
 164  * CS1 - Ext SRAM
 165  * CS2 - Available
 166  * CS3 - Available
 167  * CS4 - Available
 168  * CS5 - Available
 169  */
 170 #define CONFIG_SYS_CS0_BASE             0
 171 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 172 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 173
 174 #define CONFIG_SYS_CS1_BASE             0xC0000000
 175 #define CONFIG_SYS_CS1_MASK             0x00070001
 176 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 177
 178 #endif                          /* _M53017EVB_H */