include/configs/M53017EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF53017EVB.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M53017EVB_H
  14 #define _M53017EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_MCFUART
  22 #define CONFIG_SYS_UART_PORT            (0)
  23
  24 #undef CONFIG_WATCHDOG
  25 #define CONFIG_WATCHDOG_TIMEOUT         5000
  26
  27 #define CONFIG_SYS_UNIFY_CACHE
  28
  29 #ifdef CONFIG_MCFFEC
  30 #       define CONFIG_MII_INIT          1
  31 #       define CONFIG_SYS_DISCOVER_PHY
  32 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  33 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  34 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  35 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36 #       define CONFIG_HAS_ETH1
  37
  38 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  39 #       ifndef CONFIG_SYS_DISCOVER_PHY
  40 #               define FECDUPLEX        FULL
  41 #               define FECSPEED         _100BASET
  42 #       else
  43 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45 #               endif
  46 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  47 #endif
  48
  49 #define CONFIG_MCFRTC
  50 #undef RTC_DEBUG
  51 #define CONFIG_SYS_RTC_CNT              (0x8000)
  52 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  53
  54 /* Timer */
  55 #define CONFIG_MCFTMR
  56
  57 /* I2C */
  58 #define CONFIG_SYS_I2C_LEGACY
  59 #define CONFIG_SYS_I2C_FSL
  60 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  61 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  62 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  63 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  64
  65 #define CONFIG_UDP_CHECKSUM
  66
  67 #ifdef CONFIG_MCFFEC
  68 #       define CONFIG_IPADDR    192.162.1.2
  69 #       define CONFIG_NETMASK   255.255.255.0
  70 #       define CONFIG_SERVERIP  192.162.1.1
  71 #       define CONFIG_GATEWAYIP 192.162.1.1
  72 #endif                          /* FEC_ENET */
  73
  74 #define CONFIG_HOSTNAME         "M53017"
  75 #define CONFIG_EXTRA_ENV_SETTINGS               \
  76         "netdev=eth0\0"                         \
  77         "loadaddr=40010000\0"                   \
  78         "u-boot=u-boot.bin\0"                   \
  79         "load=tftp ${loadaddr) ${u-boot}\0"     \
  80         "upd=run load; run prog\0"              \
  81         "prog=prot off 0 3ffff;"                \
  82         "era 0 3ffff;"                          \
  83         "cp.b ${loadaddr} 0 ${filesize};"       \
  84         "save\0"                                \
  85         ""
  86
  87 #define CONFIG_PRAM             512     /* 512 KB */
  88
  89 #define CONFIG_SYS_LOAD_ADDR    0x40010000
  90
  91 #define CONFIG_SYS_CLK          80000000
  92 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
  93
  94 #define CONFIG_SYS_MBAR         0xFC000000
  95
  96 /*
  97  * Low Level Configuration Settings
  98  * (address mappings, register initial values, etc.)
  99  * You should know what you are doing if you make changes here.
 100  */
 101 /*
 102  * Definitions for initial stack pointer and data area (in DPRAM)
 103  */
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 105 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 106 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 107 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 108 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 109
 110 /*
 111  * Start addresses for the final memory configuration
 112  * (Set up by the startup code)
 113  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 114  */
 115 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 116 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 117 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 118 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 119 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 120 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 121 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 122
 123 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 124 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 125
 126 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 127 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 128
 129 /*
 130  * For booting Linux, the board info and command line data
 131  * have to be in the first 8 MB of memory, since this is
 132  * the maximum mapped by the Linux kernel during initialization ??
 133  */
 134 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 135 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 136
 137 /*-----------------------------------------------------------------------
 138  * FLASH organization
 139  */
 140 #ifdef CONFIG_SYS_FLASH_CFI
 141 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 142 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 143 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 144 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 145 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 146 #endif
 147
 148 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 149
 150 /* Configuration for environment
 151  * Environment is embedded in u-boot in the second sector of the flash
 152  */
 153
 154 #define LDS_BOARD_TEXT \
 155         . = DEFINED(env_offset) ? env_offset : .; \
 156         env/embedded.o(.text*)
 157
 158 /*-----------------------------------------------------------------------
 159  * Cache Configuration
 160  */
 161 #define CONFIG_SYS_CACHELINE_SIZE       16
 162
 163 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 164                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 165 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 166                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 167 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 168 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 169                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 170                                          CF_ACR_EN | CF_ACR_SM_ALL)
 171 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 172                                          CF_CACR_DCM_P)
 173
 174 /*-----------------------------------------------------------------------
 175  * Chipselect bank definitions
 176  */
 177 /*
 178  * CS0 - NOR Flash
 179  * CS1 - Ext SRAM
 180  * CS2 - Available
 181  * CS3 - Available
 182  * CS4 - Available
 183  * CS5 - Available
 184  */
 185 #define CONFIG_SYS_CS0_BASE             0
 186 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 187 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 188
 189 #define CONFIG_SYS_CS1_BASE             0xC0000000
 190 #define CONFIG_SYS_CS1_MASK             0x00070001
 191 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 192
 193 #endif                          /* _M53017EVB_H */