1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF53017EVB.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000
25 #define CONFIG_SYS_UNIFY_CACHE
28 # define CONFIG_MII_INIT 1
29 # define CONFIG_SYS_DISCOVER_PHY
30 # define CONFIG_SYS_RX_ETH_BUFFER 8
31 # define CONFIG_SYS_TX_ETH_BUFFER 8
32 # define CONFIG_SYS_FEC_BUF_USE_SRAM
33 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
34 # define CONFIG_HAS_ETH1
36 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
37 # ifndef CONFIG_SYS_DISCOVER_PHY
38 # define FECDUPLEX FULL
39 # define FECSPEED _100BASET
41 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 # endif /* CONFIG_SYS_DISCOVER_PHY */
49 #define CONFIG_SYS_RTC_CNT (0x8000)
50 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
56 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
58 #define CONFIG_UDP_CHECKSUM
61 # define CONFIG_IPADDR 192.162.1.2
62 # define CONFIG_NETMASK 255.255.255.0
63 # define CONFIG_SERVERIP 192.162.1.1
64 # define CONFIG_GATEWAYIP 192.162.1.1
67 #define CONFIG_HOSTNAME "M53017"
68 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "loadaddr=40010000\0" \
71 "u-boot=u-boot.bin\0" \
72 "load=tftp ${loadaddr) ${u-boot}\0" \
73 "upd=run load; run prog\0" \
74 "prog=prot off 0 3ffff;" \
76 "cp.b ${loadaddr} 0 ${filesize};" \
80 #define CONFIG_PRAM 512 /* 512 KB */
82 #define CONFIG_SYS_CLK 80000000
83 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
85 #define CONFIG_SYS_MBAR 0xFC000000
88 * Low Level Configuration Settings
89 * (address mappings, register initial values, etc.)
90 * You should know what you are doing if you make changes here.
93 * Definitions for initial stack pointer and data area (in DPRAM)
95 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
96 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
97 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
98 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
99 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
102 * Start addresses for the final memory configuration
103 * (Set up by the startup code)
104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
106 #define CONFIG_SYS_SDRAM_BASE 0x40000000
107 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
108 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
109 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
110 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
111 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
112 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
114 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
115 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
117 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
120 * For booting Linux, the board info and command line data
121 * have to be in the first 8 MB of memory, since this is
122 * the maximum mapped by the Linux kernel during initialization ??
124 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
125 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
127 /*-----------------------------------------------------------------------
130 #ifdef CONFIG_SYS_FLASH_CFI
131 # define CONFIG_FLASH_SPANSION_S29WS_N 1
132 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
133 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
134 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
135 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
138 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
140 /* Configuration for environment
141 * Environment is embedded in u-boot in the second sector of the flash
144 #define LDS_BOARD_TEXT \
145 . = DEFINED(env_offset) ? env_offset : .; \
146 env/embedded.o(.text*)
148 /*-----------------------------------------------------------------------
149 * Cache Configuration
152 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
153 CONFIG_SYS_INIT_RAM_SIZE - 8)
154 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
155 CONFIG_SYS_INIT_RAM_SIZE - 4)
156 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
157 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
158 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
159 CF_ACR_EN | CF_ACR_SM_ALL)
160 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
163 /*-----------------------------------------------------------------------
164 * Chipselect bank definitions
174 #define CONFIG_SYS_CS0_BASE 0
175 #define CONFIG_SYS_CS0_MASK 0x00FF0001
176 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
178 #define CONFIG_SYS_CS1_BASE 0xC0000000
179 #define CONFIG_SYS_CS1_MASK 0x00070001
180 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
182 #endif /* _M53017EVB_H */