1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF53017EVB.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000
25 #define CONFIG_SYS_UNIFY_CACHE
28 # define CONFIG_SYS_DISCOVER_PHY
29 # define CONFIG_SYS_TX_ETH_BUFFER 8
30 # define CONFIG_SYS_FEC_BUF_USE_SRAM
32 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
33 # ifndef CONFIG_SYS_DISCOVER_PHY
34 # define FECDUPLEX FULL
35 # define FECSPEED _100BASET
36 # endif /* CONFIG_SYS_DISCOVER_PHY */
39 #define CONFIG_SYS_RTC_CNT (0x8000)
40 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
45 # define CONFIG_IPADDR 192.162.1.2
46 # define CONFIG_NETMASK 255.255.255.0
47 # define CONFIG_SERVERIP 192.162.1.1
48 # define CONFIG_GATEWAYIP 192.162.1.1
51 #define CONFIG_HOSTNAME "M53017"
52 #define CONFIG_EXTRA_ENV_SETTINGS \
54 "loadaddr=40010000\0" \
55 "u-boot=u-boot.bin\0" \
56 "load=tftp ${loadaddr) ${u-boot}\0" \
57 "upd=run load; run prog\0" \
58 "prog=prot off 0 3ffff;" \
60 "cp.b ${loadaddr} 0 ${filesize};" \
64 #define CONFIG_PRAM 512 /* 512 KB */
66 #define CONFIG_SYS_CLK 80000000
67 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
69 #define CONFIG_SYS_MBAR 0xFC000000
72 * Low Level Configuration Settings
73 * (address mappings, register initial values, etc.)
74 * You should know what you are doing if you make changes here.
77 * Definitions for initial stack pointer and data area (in DPRAM)
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
80 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
81 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
82 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
83 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86 * Start addresses for the final memory configuration
87 * (Set up by the startup code)
88 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
90 #define CONFIG_SYS_SDRAM_BASE 0x40000000
91 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
92 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
93 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
94 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
95 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
96 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
98 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
100 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
103 * For booting Linux, the board info and command line data
104 * have to be in the first 8 MB of memory, since this is
105 * the maximum mapped by the Linux kernel during initialization ??
107 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
108 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
110 /*-----------------------------------------------------------------------
113 #ifdef CONFIG_SYS_FLASH_CFI
114 # define CONFIG_FLASH_SPANSION_S29WS_N 1
115 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
116 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
117 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
120 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
122 /* Configuration for environment
123 * Environment is embedded in u-boot in the second sector of the flash
126 #define LDS_BOARD_TEXT \
127 . = DEFINED(env_offset) ? env_offset : .; \
128 env/embedded.o(.text*)
130 /*-----------------------------------------------------------------------
131 * Cache Configuration
134 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
135 CONFIG_SYS_INIT_RAM_SIZE - 8)
136 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
137 CONFIG_SYS_INIT_RAM_SIZE - 4)
138 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
139 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
140 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
141 CF_ACR_EN | CF_ACR_SM_ALL)
142 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
145 /*-----------------------------------------------------------------------
146 * Chipselect bank definitions
156 #define CONFIG_SYS_CS0_BASE 0
157 #define CONFIG_SYS_CS0_MASK 0x00FF0001
158 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
160 #define CONFIG_SYS_CS1_BASE 0xC0000000
161 #define CONFIG_SYS_CS1_MASK 0x00070001
162 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
164 #endif /* _M53017EVB_H */