1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF53017EVB.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000
25 #define CONFIG_SYS_UNIFY_CACHE
28 # define CONFIG_MII_INIT 1
29 # define CONFIG_SYS_DISCOVER_PHY
30 # define CONFIG_SYS_RX_ETH_BUFFER 8
31 # define CONFIG_SYS_TX_ETH_BUFFER 8
32 # define CONFIG_SYS_FEC_BUF_USE_SRAM
33 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
35 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
36 # ifndef CONFIG_SYS_DISCOVER_PHY
37 # define FECDUPLEX FULL
38 # define FECSPEED _100BASET
40 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 # endif /* CONFIG_SYS_DISCOVER_PHY */
48 #define CONFIG_SYS_RTC_CNT (0x8000)
49 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
57 # define CONFIG_IPADDR 192.162.1.2
58 # define CONFIG_NETMASK 255.255.255.0
59 # define CONFIG_SERVERIP 192.162.1.1
60 # define CONFIG_GATEWAYIP 192.162.1.1
63 #define CONFIG_HOSTNAME "M53017"
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "loadaddr=40010000\0" \
67 "u-boot=u-boot.bin\0" \
68 "load=tftp ${loadaddr) ${u-boot}\0" \
69 "upd=run load; run prog\0" \
70 "prog=prot off 0 3ffff;" \
72 "cp.b ${loadaddr} 0 ${filesize};" \
76 #define CONFIG_PRAM 512 /* 512 KB */
78 #define CONFIG_SYS_CLK 80000000
79 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
81 #define CONFIG_SYS_MBAR 0xFC000000
84 * Low Level Configuration Settings
85 * (address mappings, register initial values, etc.)
86 * You should know what you are doing if you make changes here.
89 * Definitions for initial stack pointer and data area (in DPRAM)
91 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
92 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
93 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
94 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
95 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
98 * Start addresses for the final memory configuration
99 * (Set up by the startup code)
100 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
102 #define CONFIG_SYS_SDRAM_BASE 0x40000000
103 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
104 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
105 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
106 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
107 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
108 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
110 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
111 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
113 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
116 * For booting Linux, the board info and command line data
117 * have to be in the first 8 MB of memory, since this is
118 * the maximum mapped by the Linux kernel during initialization ??
120 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
121 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
123 /*-----------------------------------------------------------------------
126 #ifdef CONFIG_SYS_FLASH_CFI
127 # define CONFIG_FLASH_SPANSION_S29WS_N 1
128 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
129 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
130 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
133 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
135 /* Configuration for environment
136 * Environment is embedded in u-boot in the second sector of the flash
139 #define LDS_BOARD_TEXT \
140 . = DEFINED(env_offset) ? env_offset : .; \
141 env/embedded.o(.text*)
143 /*-----------------------------------------------------------------------
144 * Cache Configuration
147 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
148 CONFIG_SYS_INIT_RAM_SIZE - 8)
149 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
150 CONFIG_SYS_INIT_RAM_SIZE - 4)
151 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
152 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
153 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
154 CF_ACR_EN | CF_ACR_SM_ALL)
155 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
158 /*-----------------------------------------------------------------------
159 * Chipselect bank definitions
169 #define CONFIG_SYS_CS0_BASE 0
170 #define CONFIG_SYS_CS0_MASK 0x00FF0001
171 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
173 #define CONFIG_SYS_CS1_BASE 0xC0000000
174 #define CONFIG_SYS_CS1_MASK 0x00070001
175 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
177 #endif /* _M53017EVB_H */