include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  24
  25 /* Configuration for environment
  26  * Environment is embedded in u-boot in the second sector of the flash
  27  */
  28
  29 #define LDS_BOARD_TEXT \
  30         . = DEFINED(env_offset) ? env_offset : .; \
  31         env/embedded.o(.text*);
  32
  33 #ifdef CONFIG_MCFFEC
  34 #       define CONFIG_MII_INIT          1
  35 #       define CONFIG_SYS_DISCOVER_PHY
  36 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  37 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  38 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  39 #       ifndef CONFIG_SYS_DISCOVER_PHY
  40 #               define FECDUPLEX        FULL
  41 #               define FECSPEED         _100BASET
  42 #       else
  43 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45 #               endif
  46 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  47 #endif
  48
  49 #ifdef CONFIG_MCFFEC
  50 #       define CONFIG_IPADDR    192.162.1.2
  51 #       define CONFIG_NETMASK   255.255.255.0
  52 #       define CONFIG_SERVERIP  192.162.1.1
  53 #       define CONFIG_GATEWAYIP 192.162.1.1
  54 #endif                          /* CONFIG_MCFFEC */
  55
  56 #define CONFIG_HOSTNAME         "M5282EVB"
  57 #define CONFIG_EXTRA_ENV_SETTINGS               \
  58         "netdev=eth0\0"                         \
  59         "loadaddr=10000\0"                      \
  60         "u-boot=u-boot.bin\0"                   \
  61         "load=tftp ${loadaddr) ${u-boot}\0"     \
  62         "upd=run load; run prog\0"              \
  63         "prog=prot off ffe00000 ffe3ffff;"      \
  64         "era ffe00000 ffe3ffff;"                \
  65         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  66         "save\0"                                \
  67         ""
  68
  69 #define CONFIG_SYS_CLK                  64000000
  70
  71 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  72
  73 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  74 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  75
  76 /*
  77  * Low Level Configuration Settings
  78  * (address mappings, register initial values, etc.)
  79  * You should know what you are doing if you make changes here.
  80  */
  81 #define CONFIG_SYS_MBAR         0x40000000
  82
  83 /*-----------------------------------------------------------------------
  84  * Definitions for initial stack pointer and data area (in DPRAM)
  85  */
  86 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  87 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
  88 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  89 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  90
  91 /*-----------------------------------------------------------------------
  92  * Start addresses for the final memory configuration
  93  * (Set up by the startup code)
  94  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  95  */
  96 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  97 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
  98 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  99 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 100 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 101
 102 /* If M5282 port is fully implemented the monitor base will be behind
 103  * the vector table. */
 104 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 105 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 106 #else
 107 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 108 #endif
 109
 110 #define CONFIG_SYS_MONITOR_LEN          0x20000
 111 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 112
 113 /*
 114  * For booting Linux, the board info and command line data
 115  * have to be in the first 8 MB of memory, since this is
 116  * the maximum mapped by the Linux kernel during initialization ??
 117  */
 118 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 119
 120 /*-----------------------------------------------------------------------
 121  * FLASH organization
 122  */
 123 #ifdef CONFIG_SYS_FLASH_CFI
 124
 125 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 126 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 127 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 128 #       define CONFIG_SYS_FLASH_CHECKSUM
 129 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 130 #endif
 131
 132 /*-----------------------------------------------------------------------
 133  * Cache Configuration
 134  */
 135
 136 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 137                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 138 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 139                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 140 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 141 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 142                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 143                                          CF_ACR_EN | CF_ACR_SM_ALL)
 144 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 145                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 146                                          CF_CACR_EUSP)
 147
 148 /*-----------------------------------------------------------------------
 149  * Memory bank definitions
 150  */
 151 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 152 #define CONFIG_SYS_CS0_CTRL             0x00001980
 153 #define CONFIG_SYS_CS0_MASK             0x001F0001
 154
 155 /*-----------------------------------------------------------------------
 156  * Port configuration
 157  */
 158 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 159 #define CONFIG_SYS_PADDR                0x0000000
 160 #define CONFIG_SYS_PADAT                0x0000000
 161
 162 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 163 #define CONFIG_SYS_PBDDR                0x0000000
 164 #define CONFIG_SYS_PBDAT                0x0000000
 165
 166 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 167 #define CONFIG_SYS_PCDDR                0x0000000
 168 #define CONFIG_SYS_PCDAT                0x0000000
 169
 170 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 171 #define CONFIG_SYS_PCDDR                0x0000000
 172 #define CONFIG_SYS_PCDAT                0x0000000
 173
 174 #define CONFIG_SYS_PEHLPAR              0xC0
 175 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 176 #define CONFIG_SYS_DDRUA                0x05
 177 #define CONFIG_SYS_PJPAR                0xFF
 178
 179 #endif                          /* _CONFIG_M5282EVB_H */