include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_MCFUART
  22 #define CONFIG_SYS_UART_PORT            (0)
  23
  24 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  25
  26 /* Configuration for environment
  27  * Environment is embedded in u-boot in the second sector of the flash
  28  */
  29 #define CONFIG_ENV_ADDR         0xffe04000
  30 #define CONFIG_ENV_SIZE         0x2000
  31
  32 #define LDS_BOARD_TEXT \
  33         . = DEFINED(env_offset) ? env_offset : .; \
  34         env/embedded.o(.text*);
  35
  36 /*
  37  * BOOTP options
  38  */
  39 #define CONFIG_BOOTP_BOOTFILESIZE
  40
  41 /*
  42  * Command line configuration.
  43  */
  44
  45 #define CONFIG_MCFFEC
  46 #ifdef CONFIG_MCFFEC
  47 #       define CONFIG_MII               1
  48 #       define CONFIG_MII_INIT          1
  49 #       define CONFIG_SYS_DISCOVER_PHY
  50 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  51 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  52
  53 #       define CONFIG_SYS_FEC0_PINMUX           0
  54 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  55 #       define MCFFEC_TOUT_LOOP         50000
  56 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  57 #       ifndef CONFIG_SYS_DISCOVER_PHY
  58 #               define FECDUPLEX        FULL
  59 #               define FECSPEED         _100BASET
  60 #       else
  61 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  62 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  63 #               endif
  64 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  65 #endif
  66
  67 #ifdef CONFIG_MCFFEC
  68 #       define CONFIG_IPADDR    192.162.1.2
  69 #       define CONFIG_NETMASK   255.255.255.0
  70 #       define CONFIG_SERVERIP  192.162.1.1
  71 #       define CONFIG_GATEWAYIP 192.162.1.1
  72 #endif                          /* CONFIG_MCFFEC */
  73
  74 #define CONFIG_HOSTNAME         "M5282EVB"
  75 #define CONFIG_EXTRA_ENV_SETTINGS               \
  76         "netdev=eth0\0"                         \
  77         "loadaddr=10000\0"                      \
  78         "u-boot=u-boot.bin\0"                   \
  79         "load=tftp ${loadaddr) ${u-boot}\0"     \
  80         "upd=run load; run prog\0"              \
  81         "prog=prot off ffe00000 ffe3ffff;"      \
  82         "era ffe00000 ffe3ffff;"                \
  83         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  84         "save\0"                                \
  85         ""
  86
  87 #define CONFIG_SYS_LOAD_ADDR            0x20000
  88
  89 #define CONFIG_SYS_MEMTEST_START        0x400
  90 #define CONFIG_SYS_MEMTEST_END          0x380000
  91
  92 #define CONFIG_SYS_CLK                  64000000
  93
  94 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  95
  96 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  97 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  98
  99 /*
 100  * Low Level Configuration Settings
 101  * (address mappings, register initial values, etc.)
 102  * You should know what you are doing if you make changes here.
 103  */
 104 #define CONFIG_SYS_MBAR         0x40000000
 105
 106 /*-----------------------------------------------------------------------
 107  * Definitions for initial stack pointer and data area (in DPRAM)
 108  */
 109 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 110 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
 111 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 113
 114 /*-----------------------------------------------------------------------
 115  * Start addresses for the final memory configuration
 116  * (Set up by the startup code)
 117  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 118  */
 119 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 120 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 121 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 122 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 123 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 124
 125 /* If M5282 port is fully implemented the monitor base will be behind
 126  * the vector table. */
 127 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 128 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 129 #else
 130 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 131 #endif
 132
 133 #define CONFIG_SYS_MONITOR_LEN          0x20000
 134 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 135 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 136
 137 /*
 138  * For booting Linux, the board info and command line data
 139  * have to be in the first 8 MB of memory, since this is
 140  * the maximum mapped by the Linux kernel during initialization ??
 141  */
 142 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 143
 144 /*-----------------------------------------------------------------------
 145  * FLASH organization
 146  */
 147 #define CONFIG_SYS_FLASH_CFI
 148 #ifdef CONFIG_SYS_FLASH_CFI
 149
 150 #       define CONFIG_FLASH_CFI_DRIVER  1
 151 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 152 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 153 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 154 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 155 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 156 #       define CONFIG_SYS_FLASH_CHECKSUM
 157 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 158 #endif
 159
 160 /*-----------------------------------------------------------------------
 161  * Cache Configuration
 162  */
 163 #define CONFIG_SYS_CACHELINE_SIZE       16
 164
 165 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 166                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 167 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 168                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 169 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 170 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 171                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 172                                          CF_ACR_EN | CF_ACR_SM_ALL)
 173 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 174                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 175                                          CF_CACR_EUSP)
 176
 177 /*-----------------------------------------------------------------------
 178  * Memory bank definitions
 179  */
 180 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 181 #define CONFIG_SYS_CS0_CTRL             0x00001980
 182 #define CONFIG_SYS_CS0_MASK             0x001F0001
 183
 184 /*-----------------------------------------------------------------------
 185  * Port configuration
 186  */
 187 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 188 #define CONFIG_SYS_PADDR                0x0000000
 189 #define CONFIG_SYS_PADAT                0x0000000
 190
 191 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 192 #define CONFIG_SYS_PBDDR                0x0000000
 193 #define CONFIG_SYS_PBDAT                0x0000000
 194
 195 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 196 #define CONFIG_SYS_PCDDR                0x0000000
 197 #define CONFIG_SYS_PCDAT                0x0000000
 198
 199 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 200 #define CONFIG_SYS_PCDDR                0x0000000
 201 #define CONFIG_SYS_PCDAT                0x0000000
 202
 203 #define CONFIG_SYS_PEHLPAR              0xC0
 204 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 205 #define CONFIG_SYS_DDRUA                0x05
 206 #define CONFIG_SYS_PJPAR                0xFF
 207
 208 #endif                          /* _CONFIG_M5282EVB_H */