include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  24
  25 /* Configuration for environment
  26  * Environment is embedded in u-boot in the second sector of the flash
  27  */
  28
  29 #define LDS_BOARD_TEXT \
  30         . = DEFINED(env_offset) ? env_offset : .; \
  31         env/embedded.o(.text*);
  32
  33 #ifdef CONFIG_MCFFEC
  34 #       define CONFIG_MII_INIT          1
  35 #       define CONFIG_SYS_DISCOVER_PHY
  36 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  37 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  38 #       ifndef CONFIG_SYS_DISCOVER_PHY
  39 #               define FECDUPLEX        FULL
  40 #               define FECSPEED         _100BASET
  41 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  42 #endif
  43
  44 #ifdef CONFIG_MCFFEC
  45 #       define CONFIG_IPADDR    192.162.1.2
  46 #       define CONFIG_NETMASK   255.255.255.0
  47 #       define CONFIG_SERVERIP  192.162.1.1
  48 #       define CONFIG_GATEWAYIP 192.162.1.1
  49 #endif                          /* CONFIG_MCFFEC */
  50
  51 #define CONFIG_HOSTNAME         "M5282EVB"
  52 #define CONFIG_EXTRA_ENV_SETTINGS               \
  53         "netdev=eth0\0"                         \
  54         "loadaddr=10000\0"                      \
  55         "u-boot=u-boot.bin\0"                   \
  56         "load=tftp ${loadaddr) ${u-boot}\0"     \
  57         "upd=run load; run prog\0"              \
  58         "prog=prot off ffe00000 ffe3ffff;"      \
  59         "era ffe00000 ffe3ffff;"                \
  60         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  61         "save\0"                                \
  62         ""
  63
  64 #define CONFIG_SYS_CLK                  64000000
  65
  66 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  67
  68 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  69 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  70
  71 /*
  72  * Low Level Configuration Settings
  73  * (address mappings, register initial values, etc.)
  74  * You should know what you are doing if you make changes here.
  75  */
  76 #define CONFIG_SYS_MBAR         0x40000000
  77
  78 /*-----------------------------------------------------------------------
  79  * Definitions for initial stack pointer and data area (in DPRAM)
  80  */
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  84 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  85
  86 /*-----------------------------------------------------------------------
  87  * Start addresses for the final memory configuration
  88  * (Set up by the startup code)
  89  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  90  */
  91 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  92 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
  93 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  94 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
  95 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
  96
  97 /* If M5282 port is fully implemented the monitor base will be behind
  98  * the vector table. */
  99 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 100 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 101 #else
 102 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 103 #endif
 104
 105 #define CONFIG_SYS_MONITOR_LEN          0x20000
 106 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 107
 108 /*
 109  * For booting Linux, the board info and command line data
 110  * have to be in the first 8 MB of memory, since this is
 111  * the maximum mapped by the Linux kernel during initialization ??
 112  */
 113 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 114
 115 /*-----------------------------------------------------------------------
 116  * FLASH organization
 117  */
 118 #ifdef CONFIG_SYS_FLASH_CFI
 119
 120 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 121 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 122 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 123 #       define CONFIG_SYS_FLASH_CHECKSUM
 124 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 125 #endif
 126
 127 /*-----------------------------------------------------------------------
 128  * Cache Configuration
 129  */
 130
 131 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 132                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 133 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 134                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 135 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 136 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 137                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 138                                          CF_ACR_EN | CF_ACR_SM_ALL)
 139 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 140                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 141                                          CF_CACR_EUSP)
 142
 143 /*-----------------------------------------------------------------------
 144  * Memory bank definitions
 145  */
 146 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 147 #define CONFIG_SYS_CS0_CTRL             0x00001980
 148 #define CONFIG_SYS_CS0_MASK             0x001F0001
 149
 150 /*-----------------------------------------------------------------------
 151  * Port configuration
 152  */
 153 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 154 #define CONFIG_SYS_PADDR                0x0000000
 155 #define CONFIG_SYS_PADAT                0x0000000
 156
 157 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 158 #define CONFIG_SYS_PBDDR                0x0000000
 159 #define CONFIG_SYS_PBDAT                0x0000000
 160
 161 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 162 #define CONFIG_SYS_PCDDR                0x0000000
 163 #define CONFIG_SYS_PCDAT                0x0000000
 164
 165 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 166 #define CONFIG_SYS_PCDDR                0x0000000
 167 #define CONFIG_SYS_PCDAT                0x0000000
 168
 169 #define CONFIG_SYS_PEHLPAR              0xC0
 170 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 171 #define CONFIG_SYS_DDRUA                0x05
 172 #define CONFIG_SYS_PJPAR                0xFF
 173
 174 #endif                          /* _CONFIG_M5282EVB_H */