include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  24
  25 /* Configuration for environment
  26  * Environment is embedded in u-boot in the second sector of the flash
  27  */
  28
  29 #define LDS_BOARD_TEXT \
  30         . = DEFINED(env_offset) ? env_offset : .; \
  31         env/embedded.o(.text*);
  32
  33 #ifdef CONFIG_MCFFEC
  34 #       define CONFIG_MII_INIT          1
  35 #       define CONFIG_SYS_DISCOVER_PHY
  36 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  37 #       ifndef CONFIG_SYS_DISCOVER_PHY
  38 #               define FECDUPLEX        FULL
  39 #               define FECSPEED         _100BASET
  40 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  41 #endif
  42
  43 #ifdef CONFIG_MCFFEC
  44 #       define CONFIG_IPADDR    192.162.1.2
  45 #       define CONFIG_NETMASK   255.255.255.0
  46 #       define CONFIG_SERVERIP  192.162.1.1
  47 #       define CONFIG_GATEWAYIP 192.162.1.1
  48 #endif                          /* CONFIG_MCFFEC */
  49
  50 #define CONFIG_HOSTNAME         "M5282EVB"
  51 #define CONFIG_EXTRA_ENV_SETTINGS               \
  52         "netdev=eth0\0"                         \
  53         "loadaddr=10000\0"                      \
  54         "u-boot=u-boot.bin\0"                   \
  55         "load=tftp ${loadaddr) ${u-boot}\0"     \
  56         "upd=run load; run prog\0"              \
  57         "prog=prot off ffe00000 ffe3ffff;"      \
  58         "era ffe00000 ffe3ffff;"                \
  59         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  60         "save\0"                                \
  61         ""
  62
  63 #define CONFIG_SYS_CLK                  64000000
  64
  65 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  66
  67 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  68 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  69
  70 /*
  71  * Low Level Configuration Settings
  72  * (address mappings, register initial values, etc.)
  73  * You should know what you are doing if you make changes here.
  74  */
  75 #define CONFIG_SYS_MBAR         0x40000000
  76
  77 /*-----------------------------------------------------------------------
  78  * Definitions for initial stack pointer and data area (in DPRAM)
  79  */
  80 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  81 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
  82 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  83 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  84
  85 /*-----------------------------------------------------------------------
  86  * Start addresses for the final memory configuration
  87  * (Set up by the startup code)
  88  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  89  */
  90 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  91 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
  92 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  93 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
  94 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
  95
  96 /* If M5282 port is fully implemented the monitor base will be behind
  97  * the vector table. */
  98 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
  99 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 100 #else
 101 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 102 #endif
 103
 104 #define CONFIG_SYS_MONITOR_LEN          0x20000
 105 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 106
 107 /*
 108  * For booting Linux, the board info and command line data
 109  * have to be in the first 8 MB of memory, since this is
 110  * the maximum mapped by the Linux kernel during initialization ??
 111  */
 112 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 113
 114 /*-----------------------------------------------------------------------
 115  * FLASH organization
 116  */
 117 #ifdef CONFIG_SYS_FLASH_CFI
 118
 119 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 120 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 121 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 122 #       define CONFIG_SYS_FLASH_CHECKSUM
 123 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 124 #endif
 125
 126 /*-----------------------------------------------------------------------
 127  * Cache Configuration
 128  */
 129
 130 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 131                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 132 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 133                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 134 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 135 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 136                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 137                                          CF_ACR_EN | CF_ACR_SM_ALL)
 138 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 139                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 140                                          CF_CACR_EUSP)
 141
 142 /*-----------------------------------------------------------------------
 143  * Memory bank definitions
 144  */
 145 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 146 #define CONFIG_SYS_CS0_CTRL             0x00001980
 147 #define CONFIG_SYS_CS0_MASK             0x001F0001
 148
 149 /*-----------------------------------------------------------------------
 150  * Port configuration
 151  */
 152 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 153 #define CONFIG_SYS_PADDR                0x0000000
 154 #define CONFIG_SYS_PADAT                0x0000000
 155
 156 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 157 #define CONFIG_SYS_PBDDR                0x0000000
 158 #define CONFIG_SYS_PBDAT                0x0000000
 159
 160 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 161 #define CONFIG_SYS_PCDDR                0x0000000
 162 #define CONFIG_SYS_PCDAT                0x0000000
 163
 164 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 165 #define CONFIG_SYS_PCDDR                0x0000000
 166 #define CONFIG_SYS_PCDAT                0x0000000
 167
 168 #define CONFIG_SYS_PEHLPAR              0xC0
 169 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 170 #define CONFIG_SYS_DDRUA                0x05
 171 #define CONFIG_SYS_PJPAR                0xFF
 172
 173 #endif                          /* _CONFIG_M5282EVB_H */