1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Motorola MC5282EVB board.
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
9 * board/config.h - configuration options, board specific
12 #ifndef _CONFIG_M5282EVB_H
13 #define _CONFIG_M5282EVB_H
16 * High Level Configuration Options
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT (0)
24 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
26 /* Configuration for environment
27 * Environment is embedded in u-boot in the second sector of the flash
30 #define LDS_BOARD_TEXT \
31 . = DEFINED(env_offset) ? env_offset : .; \
32 env/embedded.o(.text*);
37 #define CONFIG_BOOTP_BOOTFILESIZE
40 # define CONFIG_MII_INIT 1
41 # define CONFIG_SYS_DISCOVER_PHY
42 # define CONFIG_SYS_RX_ETH_BUFFER 8
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
45 # ifndef CONFIG_SYS_DISCOVER_PHY
46 # define FECDUPLEX FULL
47 # define FECSPEED _100BASET
49 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
52 # endif /* CONFIG_SYS_DISCOVER_PHY */
56 # define CONFIG_IPADDR 192.162.1.2
57 # define CONFIG_NETMASK 255.255.255.0
58 # define CONFIG_SERVERIP 192.162.1.1
59 # define CONFIG_GATEWAYIP 192.162.1.1
60 #endif /* CONFIG_MCFFEC */
62 #define CONFIG_HOSTNAME "M5282EVB"
63 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "u-boot=u-boot.bin\0" \
67 "load=tftp ${loadaddr) ${u-boot}\0" \
68 "upd=run load; run prog\0" \
69 "prog=prot off ffe00000 ffe3ffff;" \
70 "era ffe00000 ffe3ffff;" \
71 "cp.b ${loadaddr} ffe00000 ${filesize};"\
75 #define CONFIG_SYS_CLK 64000000
77 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
79 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
80 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
83 * Low Level Configuration Settings
84 * (address mappings, register initial values, etc.)
85 * You should know what you are doing if you make changes here.
87 #define CONFIG_SYS_MBAR 0x40000000
89 /*-----------------------------------------------------------------------
90 * Definitions for initial stack pointer and data area (in DPRAM)
92 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
93 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
94 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
95 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
97 /*-----------------------------------------------------------------------
98 * Start addresses for the final memory configuration
99 * (Set up by the startup code)
100 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
102 #define CONFIG_SYS_SDRAM_BASE 0x00000000
103 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
104 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
105 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
106 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
108 /* If M5282 port is fully implemented the monitor base will be behind
109 * the vector table. */
110 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
111 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
113 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
116 #define CONFIG_SYS_MONITOR_LEN 0x20000
117 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
120 * For booting Linux, the board info and command line data
121 * have to be in the first 8 MB of memory, since this is
122 * the maximum mapped by the Linux kernel during initialization ??
124 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
126 /*-----------------------------------------------------------------------
129 #ifdef CONFIG_SYS_FLASH_CFI
131 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
132 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
133 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
134 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
135 # define CONFIG_SYS_FLASH_CHECKSUM
136 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
139 /*-----------------------------------------------------------------------
140 * Cache Configuration
143 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
144 CONFIG_SYS_INIT_RAM_SIZE - 8)
145 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
146 CONFIG_SYS_INIT_RAM_SIZE - 4)
147 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
148 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
149 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
150 CF_ACR_EN | CF_ACR_SM_ALL)
151 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
152 CF_CACR_CEIB | CF_CACR_DBWE | \
155 /*-----------------------------------------------------------------------
156 * Memory bank definitions
158 #define CONFIG_SYS_CS0_BASE 0xFFE00000
159 #define CONFIG_SYS_CS0_CTRL 0x00001980
160 #define CONFIG_SYS_CS0_MASK 0x001F0001
162 /*-----------------------------------------------------------------------
165 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
166 #define CONFIG_SYS_PADDR 0x0000000
167 #define CONFIG_SYS_PADAT 0x0000000
169 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
170 #define CONFIG_SYS_PBDDR 0x0000000
171 #define CONFIG_SYS_PBDAT 0x0000000
173 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
174 #define CONFIG_SYS_PCDDR 0x0000000
175 #define CONFIG_SYS_PCDAT 0x0000000
177 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
178 #define CONFIG_SYS_PCDDR 0x0000000
179 #define CONFIG_SYS_PCDAT 0x0000000
181 #define CONFIG_SYS_PEHLPAR 0xC0
182 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
183 #define CONFIG_SYS_DDRUA 0x05
184 #define CONFIG_SYS_PJPAR 0xFF
186 #endif /* _CONFIG_M5282EVB_H */