1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Motorola MC5282EVB board.
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
9 * board/config.h - configuration options, board specific
12 #ifndef _CONFIG_M5282EVB_H
13 #define _CONFIG_M5282EVB_H
16 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
25 /* Configuration for environment
26 * Environment is embedded in u-boot in the second sector of the flash
29 #define LDS_BOARD_TEXT \
30 . = DEFINED(env_offset) ? env_offset : .; \
31 env/embedded.o(.text*);
34 # define CONFIG_SYS_DISCOVER_PHY
35 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
36 # ifndef CONFIG_SYS_DISCOVER_PHY
37 # define FECDUPLEX FULL
38 # define FECSPEED _100BASET
39 # endif /* CONFIG_SYS_DISCOVER_PHY */
43 # define CONFIG_IPADDR 192.162.1.2
44 # define CONFIG_NETMASK 255.255.255.0
45 # define CONFIG_SERVERIP 192.162.1.1
46 # define CONFIG_GATEWAYIP 192.162.1.1
47 #endif /* CONFIG_MCFFEC */
49 #define CONFIG_HOSTNAME "M5282EVB"
50 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "u-boot=u-boot.bin\0" \
54 "load=tftp ${loadaddr) ${u-boot}\0" \
55 "upd=run load; run prog\0" \
56 "prog=prot off ffe00000 ffe3ffff;" \
57 "era ffe00000 ffe3ffff;" \
58 "cp.b ${loadaddr} ffe00000 ${filesize};"\
62 #define CONFIG_SYS_CLK 64000000
64 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
66 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
67 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
70 * Low Level Configuration Settings
71 * (address mappings, register initial values, etc.)
72 * You should know what you are doing if you make changes here.
74 #define CONFIG_SYS_MBAR 0x40000000
76 /*-----------------------------------------------------------------------
77 * Definitions for initial stack pointer and data area (in DPRAM)
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
80 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
81 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
82 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
84 /*-----------------------------------------------------------------------
85 * Start addresses for the final memory configuration
86 * (Set up by the startup code)
87 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
89 #define CONFIG_SYS_SDRAM_BASE 0x00000000
90 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
91 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
92 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
93 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
95 /* If M5282 port is fully implemented the monitor base will be behind
96 * the vector table. */
97 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
98 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
100 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
103 #define CONFIG_SYS_MONITOR_LEN 0x20000
104 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
107 * For booting Linux, the board info and command line data
108 * have to be in the first 8 MB of memory, since this is
109 * the maximum mapped by the Linux kernel during initialization ??
111 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
113 /*-----------------------------------------------------------------------
116 #ifdef CONFIG_SYS_FLASH_CFI
118 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
119 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
120 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
121 # define CONFIG_SYS_FLASH_CHECKSUM
122 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
125 /*-----------------------------------------------------------------------
126 * Cache Configuration
129 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
130 CONFIG_SYS_INIT_RAM_SIZE - 8)
131 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
132 CONFIG_SYS_INIT_RAM_SIZE - 4)
133 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
134 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
135 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
136 CF_ACR_EN | CF_ACR_SM_ALL)
137 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
138 CF_CACR_CEIB | CF_CACR_DBWE | \
141 /*-----------------------------------------------------------------------
142 * Memory bank definitions
144 #define CONFIG_SYS_CS0_BASE 0xFFE00000
145 #define CONFIG_SYS_CS0_CTRL 0x00001980
146 #define CONFIG_SYS_CS0_MASK 0x001F0001
148 /*-----------------------------------------------------------------------
151 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
152 #define CONFIG_SYS_PADDR 0x0000000
153 #define CONFIG_SYS_PADAT 0x0000000
155 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
156 #define CONFIG_SYS_PBDDR 0x0000000
157 #define CONFIG_SYS_PBDAT 0x0000000
159 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
160 #define CONFIG_SYS_PCDDR 0x0000000
161 #define CONFIG_SYS_PCDAT 0x0000000
163 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
164 #define CONFIG_SYS_PCDDR 0x0000000
165 #define CONFIG_SYS_PCDAT 0x0000000
167 #define CONFIG_SYS_PEHLPAR 0xC0
168 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
169 #define CONFIG_SYS_DDRUA 0x05
170 #define CONFIG_SYS_PJPAR 0xFF
172 #endif /* _CONFIG_M5282EVB_H */