include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_SYS_UART_PORT            (0)
  21
  22 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  23
  24 /* Configuration for environment
  25  * Environment is embedded in u-boot in the second sector of the flash
  26  */
  27
  28 #define LDS_BOARD_TEXT \
  29         . = DEFINED(env_offset) ? env_offset : .; \
  30         env/embedded.o(.text*);
  31
  32 #ifdef CONFIG_MCFFEC
  33 #       define CONFIG_SYS_DISCOVER_PHY
  34 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  35 #       ifndef CONFIG_SYS_DISCOVER_PHY
  36 #               define FECDUPLEX        FULL
  37 #               define FECSPEED         _100BASET
  38 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  39 #endif
  40
  41 #ifdef CONFIG_MCFFEC
  42 #       define CONFIG_IPADDR    192.162.1.2
  43 #       define CONFIG_NETMASK   255.255.255.0
  44 #       define CONFIG_SERVERIP  192.162.1.1
  45 #       define CONFIG_GATEWAYIP 192.162.1.1
  46 #endif                          /* CONFIG_MCFFEC */
  47
  48 #define CONFIG_HOSTNAME         "M5282EVB"
  49 #define CONFIG_EXTRA_ENV_SETTINGS               \
  50         "netdev=eth0\0"                         \
  51         "loadaddr=10000\0"                      \
  52         "u-boot=u-boot.bin\0"                   \
  53         "load=tftp ${loadaddr) ${u-boot}\0"     \
  54         "upd=run load; run prog\0"              \
  55         "prog=prot off ffe00000 ffe3ffff;"      \
  56         "era ffe00000 ffe3ffff;"                \
  57         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  58         "save\0"                                \
  59         ""
  60
  61 #define CONFIG_SYS_CLK                  64000000
  62
  63 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  64
  65 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  66 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  67
  68 /*
  69  * Low Level Configuration Settings
  70  * (address mappings, register initial values, etc.)
  71  * You should know what you are doing if you make changes here.
  72  */
  73 #define CONFIG_SYS_MBAR         0x40000000
  74
  75 /*-----------------------------------------------------------------------
  76  * Definitions for initial stack pointer and data area (in DPRAM)
  77  */
  78 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  79 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
  80
  81 /*-----------------------------------------------------------------------
  82  * Start addresses for the final memory configuration
  83  * (Set up by the startup code)
  84  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  85  */
  86 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  87 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
  88 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  89 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
  90 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
  91
  92 #define CONFIG_SYS_MONITOR_LEN          0x20000
  93
  94 /*
  95  * For booting Linux, the board info and command line data
  96  * have to be in the first 8 MB of memory, since this is
  97  * the maximum mapped by the Linux kernel during initialization ??
  98  */
  99 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 100
 101 /*-----------------------------------------------------------------------
 102  * FLASH organization
 103  */
 104 #ifdef CONFIG_SYS_FLASH_CFI
 105
 106 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 107 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 108 #       define CONFIG_SYS_FLASH_CHECKSUM
 109 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 110 #endif
 111
 112 /*-----------------------------------------------------------------------
 113  * Cache Configuration
 114  */
 115
 116 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 117                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 118 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 119                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 120 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 121 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 122                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 123                                          CF_ACR_EN | CF_ACR_SM_ALL)
 124 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 125                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 126                                          CF_CACR_EUSP)
 127
 128 /*-----------------------------------------------------------------------
 129  * Memory bank definitions
 130  */
 131 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 132 #define CONFIG_SYS_CS0_CTRL             0x00001980
 133 #define CONFIG_SYS_CS0_MASK             0x001F0001
 134
 135 /*-----------------------------------------------------------------------
 136  * Port configuration
 137  */
 138 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 139 #define CONFIG_SYS_PADDR                0x0000000
 140 #define CONFIG_SYS_PADAT                0x0000000
 141
 142 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 143 #define CONFIG_SYS_PBDDR                0x0000000
 144 #define CONFIG_SYS_PBDAT                0x0000000
 145
 146 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 147 #define CONFIG_SYS_PCDDR                0x0000000
 148 #define CONFIG_SYS_PCDAT                0x0000000
 149
 150 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 151 #define CONFIG_SYS_PCDDR                0x0000000
 152 #define CONFIG_SYS_PCDAT                0x0000000
 153
 154 #define CONFIG_SYS_PEHLPAR              0xC0
 155 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 156 #define CONFIG_SYS_DDRUA                0x05
 157 #define CONFIG_SYS_PJPAR                0xFF
 158
 159 #endif                          /* _CONFIG_M5282EVB_H */