2 * Configuation settings for the Motorola MC5275EVB board.
4 * By Arthur Shipkowski <art@videon-central.com>
5 * Copyright (C) 2005 Videon Central, Inc.
7 * Based off of M5272C3 board code by Josef Baumgartner
8 * <josef.baumgartner@telex.de>
10 * SPDX-License-Identifier: GPL-2.0+
14 * board/config.h - configuration options, board specific
21 * High Level Configuration Options
24 #define CONFIG_M5275EVB /* define board type */
28 #define CONFIG_MCFUART
29 #define CONFIG_SYS_UART_PORT (0)
30 #define CONFIG_BAUDRATE 115200
32 /* Configuration for environment
33 * Environment is embedded in u-boot in the second sector of the flash
35 #ifndef CONFIG_MONITOR_IS_IN_RAM
36 #define CONFIG_ENV_OFFSET 0x4000
37 #define CONFIG_ENV_SECT_SIZE 0x2000
38 #define CONFIG_ENV_IS_IN_FLASH 1
40 #define CONFIG_ENV_ADDR 0xffe04000
41 #define CONFIG_ENV_SECT_SIZE 0x2000
42 #define CONFIG_ENV_IS_IN_FLASH 1
45 #define LDS_BOARD_TEXT \
46 . = DEFINED(env_offset) ? env_offset : .; \
47 common/env_embedded.o (.text);
52 #define CONFIG_BOOTP_BOOTFILESIZE
53 #define CONFIG_BOOTP_BOOTPATH
54 #define CONFIG_BOOTP_GATEWAY
55 #define CONFIG_BOOTP_HOSTNAME
57 /* Available command configuration */
58 #define CONFIG_CMD_CACHE
59 #define CONFIG_CMD_PING
60 #define CONFIG_CMD_MII
61 #define CONFIG_CMD_ELF
62 #define CONFIG_CMD_I2C
63 #define CONFIG_CMD_DHCP
69 #define CONFIG_MII_INIT 1
70 #define CONFIG_SYS_DISCOVER_PHY
71 #define CONFIG_SYS_RX_ETH_BUFFER 8
72 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
73 #define CONFIG_SYS_FEC0_PINMUX 0
74 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
75 #define CONFIG_SYS_FEC1_PINMUX 0
76 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
77 #define MCFFEC_TOUT_LOOP 50000
78 #define CONFIG_HAS_ETH1
79 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
80 #ifndef CONFIG_SYS_DISCOVER_PHY
81 #define FECDUPLEX FULL
82 #define FECSPEED _100BASET
84 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
85 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
91 #define CONFIG_SYS_I2C
92 #define CONFIG_SYS_I2C_FSL
93 #define CONFIG_SYS_FSL_I2C_SPEED 80000
94 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
95 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
96 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
97 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
98 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
99 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
101 #define CONFIG_SYS_LONGHELP /* undef to save memory */
103 #if (CONFIG_CMD_KGDB)
104 # define CONFIG_SYS_CBSIZE 1024
106 # define CONFIG_SYS_CBSIZE 256
108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
109 #define CONFIG_SYS_MAXARGS 16
110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
112 #define CONFIG_SYS_LOAD_ADDR 0x800000
114 #define CONFIG_BOOTDELAY 5
115 #define CONFIG_BOOTCOMMAND "bootm ffe40000"
116 #define CONFIG_SYS_MEMTEST_START 0x400
117 #define CONFIG_SYS_MEMTEST_END 0x380000
120 # define CONFIG_NET_RETRY_COUNT 5
121 # define CONFIG_OVERWRITE_ETHADDR_ONCE
122 #endif /* FEC_ENET */
124 #define CONFIG_EXTRA_ENV_SETTINGS \
127 "uboot=u-boot.bin\0" \
128 "load=tftp ${loadaddr} ${uboot}\0" \
129 "upd=run load; run prog\0" \
130 "prog=prot off ffe00000 ffe3ffff;" \
131 "era ffe00000 ffe3ffff;" \
132 "cp.b ${loadaddr} ffe00000 ${filesize};"\
136 #define CONFIG_SYS_CLK 150000000
139 * Low Level Configuration Settings
140 * (address mappings, register initial values, etc.)
141 * You should know what you are doing if you make changes here.
144 #define CONFIG_SYS_MBAR 0x40000000
146 /*-----------------------------------------------------------------------
147 * Definitions for initial stack pointer and data area (in DPRAM)
149 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
150 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
151 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
154 /*-----------------------------------------------------------------------
155 * Start addresses for the final memory configuration
156 * (Set up by the startup code)
157 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
159 #define CONFIG_SYS_SDRAM_BASE 0x00000000
160 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
161 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
163 #ifdef CONFIG_MONITOR_IS_IN_RAM
164 #define CONFIG_SYS_MONITOR_BASE 0x20000
166 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
169 #define CONFIG_SYS_MONITOR_LEN 0x20000
170 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
171 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization ??
178 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
179 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
181 /*-----------------------------------------------------------------------
184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
186 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
188 #define CONFIG_SYS_FLASH_CFI 1
189 #define CONFIG_FLASH_CFI_DRIVER 1
190 #define CONFIG_SYS_FLASH_SIZE 0x200000
192 /*-----------------------------------------------------------------------
193 * Cache Configuration
195 #define CONFIG_SYS_CACHELINE_SIZE 16
197 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
198 CONFIG_SYS_INIT_RAM_SIZE - 8)
199 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
200 CONFIG_SYS_INIT_RAM_SIZE - 4)
201 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
202 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
203 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
204 CF_ACR_EN | CF_ACR_SM_ALL)
205 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
206 CF_CACR_DISD | CF_CACR_INVI | \
207 CF_CACR_CEIB | CF_CACR_DCM | \
210 /*-----------------------------------------------------------------------
211 * Memory bank definitions
213 #define CONFIG_SYS_CS0_BASE 0xffe00000
214 #define CONFIG_SYS_CS0_CTRL 0x00001980
215 #define CONFIG_SYS_CS0_MASK 0x001F0001
217 #define CONFIG_SYS_CS1_BASE 0x30000000
218 #define CONFIG_SYS_CS1_CTRL 0x00001900
219 #define CONFIG_SYS_CS1_MASK 0x00070001
221 /*-----------------------------------------------------------------------
224 #define CONFIG_SYS_FECI2C 0x0FA0
226 #endif /* _M5275EVB_H */