1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Motorola MC5275EVB board.
5 * By Arthur Shipkowski <art@videon-central.com>
6 * Copyright (C) 2005 Videon Central, Inc.
8 * Based off of M5272C3 board code by Josef Baumgartner
9 * <josef.baumgartner@telex.de>
13 * board/config.h - configuration options, board specific
20 * High Level Configuration Options
26 #define CONFIG_SYS_UART_PORT (0)
28 /* Configuration for environment
29 * Environment is embedded in u-boot in the second sector of the flash
32 #define LDS_BOARD_TEXT \
33 . = DEFINED(env_offset) ? env_offset : .; \
34 env/embedded.o(.text);
36 /* Available command configuration */
39 #define CONFIG_MII_INIT 1
40 #define CONFIG_SYS_DISCOVER_PHY
41 #define CONFIG_SYS_RX_ETH_BUFFER 8
42 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 #define CONFIG_HAS_ETH1
44 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
45 #ifndef CONFIG_SYS_DISCOVER_PHY
46 #define FECDUPLEX FULL
47 #define FECSPEED _100BASET
49 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
50 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
57 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
58 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
61 # define CONFIG_OVERWRITE_ETHADDR_ONCE
64 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "uboot=u-boot.bin\0" \
68 "load=tftp ${loadaddr} ${uboot}\0" \
69 "upd=run load; run prog\0" \
70 "prog=prot off ffe00000 ffe3ffff;" \
71 "era ffe00000 ffe3ffff;" \
72 "cp.b ${loadaddr} ffe00000 ${filesize};"\
76 #define CONFIG_SYS_CLK 150000000
79 * Low Level Configuration Settings
80 * (address mappings, register initial values, etc.)
81 * You should know what you are doing if you make changes here.
84 #define CONFIG_SYS_MBAR 0x40000000
86 /*-----------------------------------------------------------------------
87 * Definitions for initial stack pointer and data area (in DPRAM)
89 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
90 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
91 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
92 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
94 /*-----------------------------------------------------------------------
95 * Start addresses for the final memory configuration
96 * (Set up by the startup code)
97 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
99 #define CONFIG_SYS_SDRAM_BASE 0x00000000
100 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
101 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
103 #ifdef CONFIG_MONITOR_IS_IN_RAM
104 #define CONFIG_SYS_MONITOR_BASE 0x20000
106 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
109 #define CONFIG_SYS_MONITOR_LEN 0x20000
110 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
113 * For booting Linux, the board info and command line data
114 * have to be in the first 8 MB of memory, since this is
115 * the maximum mapped by the Linux kernel during initialization ??
117 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
118 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
120 /*-----------------------------------------------------------------------
123 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
124 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
126 #define CONFIG_SYS_FLASH_SIZE 0x200000
128 /*-----------------------------------------------------------------------
129 * Cache Configuration
132 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
133 CONFIG_SYS_INIT_RAM_SIZE - 8)
134 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
135 CONFIG_SYS_INIT_RAM_SIZE - 4)
136 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
137 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
138 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
139 CF_ACR_EN | CF_ACR_SM_ALL)
140 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
141 CF_CACR_DISD | CF_CACR_INVI | \
142 CF_CACR_CEIB | CF_CACR_DCM | \
145 /*-----------------------------------------------------------------------
146 * Memory bank definitions
148 #define CONFIG_SYS_CS0_BASE 0xffe00000
149 #define CONFIG_SYS_CS0_CTRL 0x00001980
150 #define CONFIG_SYS_CS0_MASK 0x001F0001
152 #define CONFIG_SYS_CS1_BASE 0x30000000
153 #define CONFIG_SYS_CS1_CTRL 0x00001900
154 #define CONFIG_SYS_CS1_MASK 0x00070001
156 /*-----------------------------------------------------------------------
159 #define CONFIG_SYS_FECI2C 0x0FA0
161 #endif /* _M5275EVB_H */