1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Motorola MC5275EVB board.
5 * By Arthur Shipkowski <art@videon-central.com>
6 * Copyright (C) 2005 Videon Central, Inc.
8 * Based off of M5272C3 board code by Josef Baumgartner
9 * <josef.baumgartner@telex.de>
13 * board/config.h - configuration options, board specific
20 * High Level Configuration Options
26 #define CONFIG_SYS_UART_PORT (0)
28 /* Configuration for environment
29 * Environment is embedded in u-boot in the second sector of the flash
32 #define LDS_BOARD_TEXT \
33 . = DEFINED(env_offset) ? env_offset : .; \
34 env/embedded.o(.text);
36 /* Available command configuration */
39 #define CONFIG_MII_INIT 1
40 #define CONFIG_SYS_DISCOVER_PHY
41 #define CONFIG_SYS_RX_ETH_BUFFER 8
42 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 #define CONFIG_HAS_ETH1
44 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
45 #ifndef CONFIG_SYS_DISCOVER_PHY
46 #define FECDUPLEX FULL
47 #define FECSPEED _100BASET
49 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
50 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
57 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
58 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
61 # define CONFIG_NET_RETRY_COUNT 5
62 # define CONFIG_OVERWRITE_ETHADDR_ONCE
65 #define CONFIG_EXTRA_ENV_SETTINGS \
68 "uboot=u-boot.bin\0" \
69 "load=tftp ${loadaddr} ${uboot}\0" \
70 "upd=run load; run prog\0" \
71 "prog=prot off ffe00000 ffe3ffff;" \
72 "era ffe00000 ffe3ffff;" \
73 "cp.b ${loadaddr} ffe00000 ${filesize};"\
77 #define CONFIG_SYS_CLK 150000000
80 * Low Level Configuration Settings
81 * (address mappings, register initial values, etc.)
82 * You should know what you are doing if you make changes here.
85 #define CONFIG_SYS_MBAR 0x40000000
87 /*-----------------------------------------------------------------------
88 * Definitions for initial stack pointer and data area (in DPRAM)
90 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
91 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
92 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
95 /*-----------------------------------------------------------------------
96 * Start addresses for the final memory configuration
97 * (Set up by the startup code)
98 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
100 #define CONFIG_SYS_SDRAM_BASE 0x00000000
101 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
102 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
104 #ifdef CONFIG_MONITOR_IS_IN_RAM
105 #define CONFIG_SYS_MONITOR_BASE 0x20000
107 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
110 #define CONFIG_SYS_MONITOR_LEN 0x20000
111 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
114 * For booting Linux, the board info and command line data
115 * have to be in the first 8 MB of memory, since this is
116 * the maximum mapped by the Linux kernel during initialization ??
118 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
119 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
121 /*-----------------------------------------------------------------------
124 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
125 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
127 #define CONFIG_SYS_FLASH_SIZE 0x200000
129 /*-----------------------------------------------------------------------
130 * Cache Configuration
133 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
134 CONFIG_SYS_INIT_RAM_SIZE - 8)
135 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
136 CONFIG_SYS_INIT_RAM_SIZE - 4)
137 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
138 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
139 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
140 CF_ACR_EN | CF_ACR_SM_ALL)
141 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
142 CF_CACR_DISD | CF_CACR_INVI | \
143 CF_CACR_CEIB | CF_CACR_DCM | \
146 /*-----------------------------------------------------------------------
147 * Memory bank definitions
149 #define CONFIG_SYS_CS0_BASE 0xffe00000
150 #define CONFIG_SYS_CS0_CTRL 0x00001980
151 #define CONFIG_SYS_CS0_MASK 0x001F0001
153 #define CONFIG_SYS_CS1_BASE 0x30000000
154 #define CONFIG_SYS_CS1_CTRL 0x00001900
155 #define CONFIG_SYS_CS1_MASK 0x00070001
157 /*-----------------------------------------------------------------------
160 #define CONFIG_SYS_FECI2C 0x0FA0
162 #endif /* _M5275EVB_H */