include/configs/M5275EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5275EVB board.
   4  *
   5  * By Arthur Shipkowski <art@videon-central.com>
   6  * Copyright (C) 2005 Videon Central, Inc.
   7  *
   8  * Based off of M5272C3 board code by Josef Baumgartner
   9  * <josef.baumgartner@telex.de>
  10  */
  11
  12 /*
  13  * board/config.h - configuration options, board specific
  14  */
  15
  16 #ifndef _M5275EVB_H
  17 #define _M5275EVB_H
  18
  19 /*
  20  * High Level Configuration Options
  21  * (easy to change)
  22  */
  23
  24 #define CONFIG_MCFTMR
  25
  26 #define CONFIG_MCFUART
  27 #define CONFIG_SYS_UART_PORT            (0)
  28
  29 /* Configuration for environment
  30  * Environment is embedded in u-boot in the second sector of the flash
  31  */
  32
  33 #define LDS_BOARD_TEXT \
  34         . = DEFINED(env_offset) ? env_offset : .; \
  35         env/embedded.o(.text);
  36
  37 /*
  38  * BOOTP options
  39  */
  40 #define CONFIG_BOOTP_BOOTFILESIZE
  41
  42 /* Available command configuration */
  43
  44 #ifdef CONFIG_MCFFEC
  45 #define CONFIG_MII_INIT         1
  46 #define CONFIG_SYS_DISCOVER_PHY
  47 #define CONFIG_SYS_RX_ETH_BUFFER        8
  48 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  49 #define CONFIG_HAS_ETH1
  50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  51 #ifndef CONFIG_SYS_DISCOVER_PHY
  52 #define FECDUPLEX               FULL
  53 #define FECSPEED                _100BASET
  54 #else
  55 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  56 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  57 #endif
  58 #endif
  59 #endif
  60
  61 /* I2C */
  62 #define CONFIG_SYS_I2C
  63 #define CONFIG_SYS_I2C_FSL
  64 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  65 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  66 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  67 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  68 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio_reg->par_feci2c)
  69 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFF0)
  70 #define CONFIG_SYS_I2C_PINMUX_SET       (0x000F)
  71
  72 #define CONFIG_SYS_LOAD_ADDR            0x800000
  73
  74 #define CONFIG_BOOTCOMMAND      "bootm ffe40000"
  75 #define CONFIG_SYS_MEMTEST_START        0x400
  76 #define CONFIG_SYS_MEMTEST_END          0x380000
  77
  78 #ifdef CONFIG_MCFFEC
  79 #       define CONFIG_NET_RETRY_COUNT   5
  80 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  81 #endif                          /* FEC_ENET */
  82
  83 #define CONFIG_EXTRA_ENV_SETTINGS               \
  84         "netdev=eth0\0"                         \
  85         "loadaddr=10000\0"                      \
  86         "uboot=u-boot.bin\0"                    \
  87         "load=tftp ${loadaddr} ${uboot}\0"      \
  88         "upd=run load; run prog\0"              \
  89         "prog=prot off ffe00000 ffe3ffff;"      \
  90         "era ffe00000 ffe3ffff;"                \
  91         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  92         "save\0"                                \
  93         ""
  94
  95 #define CONFIG_SYS_CLK                  150000000
  96
  97 /*
  98  * Low Level Configuration Settings
  99  * (address mappings, register initial values, etc.)
 100  * You should know what you are doing if you make changes here.
 101  */
 102
 103 #define CONFIG_SYS_MBAR         0x40000000
 104
 105 /*-----------------------------------------------------------------------
 106  * Definitions for initial stack pointer and data area (in DPRAM)
 107  */
 108 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 109 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 110 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 111 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 112
 113 /*-----------------------------------------------------------------------
 114  * Start addresses for the final memory configuration
 115  * (Set up by the startup code)
 116  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 117  */
 118 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 119 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 120 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 121
 122 #ifdef CONFIG_MONITOR_IS_IN_RAM
 123 #define CONFIG_SYS_MONITOR_BASE 0x20000
 124 #else
 125 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 126 #endif
 127
 128 #define CONFIG_SYS_MONITOR_LEN          0x20000
 129 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 130 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 131
 132 /*
 133  * For booting Linux, the board info and command line data
 134  * have to be in the first 8 MB of memory, since this is
 135  * the maximum mapped by the Linux kernel during initialization ??
 136  */
 137 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 138 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 139
 140 /*-----------------------------------------------------------------------
 141  * FLASH organization
 142  */
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 144 #define CONFIG_SYS_MAX_FLASH_SECT       11      /* max number of sectors on one chip */
 145 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 146
 147 #define CONFIG_SYS_FLASH_SIZE           0x200000
 148
 149 /*-----------------------------------------------------------------------
 150  * Cache Configuration
 151  */
 152 #define CONFIG_SYS_CACHELINE_SIZE       16
 153
 154 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 155                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 156 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 157                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 158 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 159 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 160                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 161                                          CF_ACR_EN | CF_ACR_SM_ALL)
 162 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 163                                          CF_CACR_DISD | CF_CACR_INVI | \
 164                                          CF_CACR_CEIB | CF_CACR_DCM | \
 165                                          CF_CACR_EUSP)
 166
 167 /*-----------------------------------------------------------------------
 168  * Memory bank definitions
 169  */
 170 #define CONFIG_SYS_CS0_BASE             0xffe00000
 171 #define CONFIG_SYS_CS0_CTRL             0x00001980
 172 #define CONFIG_SYS_CS0_MASK             0x001F0001
 173
 174 #define CONFIG_SYS_CS1_BASE             0x30000000
 175 #define CONFIG_SYS_CS1_CTRL             0x00001900
 176 #define CONFIG_SYS_CS1_MASK             0x00070001
 177
 178 /*-----------------------------------------------------------------------
 179  * Port configuration
 180  */
 181 #define CONFIG_SYS_FECI2C               0x0FA0
 182
 183 #endif  /* _M5275EVB_H */