include/configs/M5275EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5275EVB board.
   4  *
   5  * By Arthur Shipkowski <art@videon-central.com>
   6  * Copyright (C) 2005 Videon Central, Inc.
   7  *
   8  * Based off of M5272C3 board code by Josef Baumgartner
   9  * <josef.baumgartner@telex.de>
  10  */
  11
  12 /*
  13  * board/config.h - configuration options, board specific
  14  */
  15
  16 #ifndef _M5275EVB_H
  17 #define _M5275EVB_H
  18
  19 /*
  20  * High Level Configuration Options
  21  * (easy to change)
  22  */
  23
  24 #define CONFIG_MCFTMR
  25
  26 #define CONFIG_MCFUART
  27 #define CONFIG_SYS_UART_PORT            (0)
  28
  29 /* Configuration for environment
  30  * Environment is embedded in u-boot in the second sector of the flash
  31  */
  32 #ifndef CONFIG_MONITOR_IS_IN_RAM
  33 #define CONFIG_ENV_OFFSET               0x4000
  34 #define CONFIG_ENV_SECT_SIZE    0x2000
  35 #else
  36 #define CONFIG_ENV_ADDR         0xffe04000
  37 #define CONFIG_ENV_SECT_SIZE    0x2000
  38 #endif
  39
  40 #define LDS_BOARD_TEXT \
  41         . = DEFINED(env_offset) ? env_offset : .; \
  42         env/embedded.o(.text);
  43
  44 /*
  45  * BOOTP options
  46  */
  47 #define CONFIG_BOOTP_BOOTFILESIZE
  48
  49 /* Available command configuration */
  50
  51 #define CONFIG_MCFFEC
  52 #ifdef CONFIG_MCFFEC
  53 #define CONFIG_MII              1
  54 #define CONFIG_MII_INIT         1
  55 #define CONFIG_SYS_DISCOVER_PHY
  56 #define CONFIG_SYS_RX_ETH_BUFFER        8
  57 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  58 #define CONFIG_SYS_FEC0_PINMUX          0
  59 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  60 #define CONFIG_SYS_FEC1_PINMUX          0
  61 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
  62 #define MCFFEC_TOUT_LOOP        50000
  63 #define CONFIG_HAS_ETH1
  64 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  65 #ifndef CONFIG_SYS_DISCOVER_PHY
  66 #define FECDUPLEX               FULL
  67 #define FECSPEED                _100BASET
  68 #else
  69 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  70 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  71 #endif
  72 #endif
  73 #endif
  74
  75 /* I2C */
  76 #define CONFIG_SYS_I2C
  77 #define CONFIG_SYS_I2C_FSL
  78 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  79 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  80 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  81 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  82 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio_reg->par_feci2c)
  83 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFF0)
  84 #define CONFIG_SYS_I2C_PINMUX_SET       (0x000F)
  85
  86 #define CONFIG_SYS_LOAD_ADDR            0x800000
  87
  88 #define CONFIG_BOOTCOMMAND      "bootm ffe40000"
  89 #define CONFIG_SYS_MEMTEST_START        0x400
  90 #define CONFIG_SYS_MEMTEST_END          0x380000
  91
  92 #ifdef CONFIG_MCFFEC
  93 #       define CONFIG_NET_RETRY_COUNT   5
  94 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  95 #endif                          /* FEC_ENET */
  96
  97 #define CONFIG_EXTRA_ENV_SETTINGS               \
  98         "netdev=eth0\0"                         \
  99         "loadaddr=10000\0"                      \
 100         "uboot=u-boot.bin\0"                    \
 101         "load=tftp ${loadaddr} ${uboot}\0"      \
 102         "upd=run load; run prog\0"              \
 103         "prog=prot off ffe00000 ffe3ffff;"      \
 104         "era ffe00000 ffe3ffff;"                \
 105         "cp.b ${loadaddr} ffe00000 ${filesize};"\
 106         "save\0"                                \
 107         ""
 108
 109 #define CONFIG_SYS_CLK                  150000000
 110
 111 /*
 112  * Low Level Configuration Settings
 113  * (address mappings, register initial values, etc.)
 114  * You should know what you are doing if you make changes here.
 115  */
 116
 117 #define CONFIG_SYS_MBAR         0x40000000
 118
 119 /*-----------------------------------------------------------------------
 120  * Definitions for initial stack pointer and data area (in DPRAM)
 121  */
 122 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 123 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 124 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 125 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 126
 127 /*-----------------------------------------------------------------------
 128  * Start addresses for the final memory configuration
 129  * (Set up by the startup code)
 130  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 131  */
 132 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 133 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 134 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 135
 136 #ifdef CONFIG_MONITOR_IS_IN_RAM
 137 #define CONFIG_SYS_MONITOR_BASE 0x20000
 138 #else
 139 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 140 #endif
 141
 142 #define CONFIG_SYS_MONITOR_LEN          0x20000
 143 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 144 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 145
 146 /*
 147  * For booting Linux, the board info and command line data
 148  * have to be in the first 8 MB of memory, since this is
 149  * the maximum mapped by the Linux kernel during initialization ??
 150  */
 151 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 152 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 153
 154 /*-----------------------------------------------------------------------
 155  * FLASH organization
 156  */
 157 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 158 #define CONFIG_SYS_MAX_FLASH_SECT       11      /* max number of sectors on one chip */
 159 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 160
 161 #define CONFIG_SYS_FLASH_CFI            1
 162 #define CONFIG_FLASH_CFI_DRIVER 1
 163 #define CONFIG_SYS_FLASH_SIZE           0x200000
 164
 165 /*-----------------------------------------------------------------------
 166  * Cache Configuration
 167  */
 168 #define CONFIG_SYS_CACHELINE_SIZE       16
 169
 170 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 171                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 172 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 173                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 174 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 175 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 176                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 177                                          CF_ACR_EN | CF_ACR_SM_ALL)
 178 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 179                                          CF_CACR_DISD | CF_CACR_INVI | \
 180                                          CF_CACR_CEIB | CF_CACR_DCM | \
 181                                          CF_CACR_EUSP)
 182
 183 /*-----------------------------------------------------------------------
 184  * Memory bank definitions
 185  */
 186 #define CONFIG_SYS_CS0_BASE             0xffe00000
 187 #define CONFIG_SYS_CS0_CTRL             0x00001980
 188 #define CONFIG_SYS_CS0_MASK             0x001F0001
 189
 190 #define CONFIG_SYS_CS1_BASE             0x30000000
 191 #define CONFIG_SYS_CS1_CTRL             0x00001900
 192 #define CONFIG_SYS_CS1_MASK             0x00070001
 193
 194 /*-----------------------------------------------------------------------
 195  * Port configuration
 196  */
 197 #define CONFIG_SYS_FECI2C               0x0FA0
 198
 199 #endif  /* _M5275EVB_H */