include/configs/M5272C3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5272C3 board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _M5272C3_H
  13 #define _M5272C3_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CFG_SYS_UART_PORT               (0)
  21
  22 #define CONFIG_WATCHDOG_TIMEOUT 10000   /* timeout in milliseconds */
  23
  24 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  25
  26 /* Configuration for environment
  27  * Environment is embedded in u-boot in the second sector of the flash
  28  */
  29
  30 #define LDS_BOARD_TEXT \
  31         . = DEFINED(env_offset) ? env_offset : .; \
  32         env/embedded.o(.text);
  33
  34 #ifdef CONFIG_MCFFEC
  35 #       define CONFIG_IPADDR    192.162.1.2
  36 #       define CONFIG_NETMASK   255.255.255.0
  37 #       define CONFIG_SERVERIP  192.162.1.1
  38 #       define CONFIG_GATEWAYIP 192.162.1.1
  39 #endif                          /* CONFIG_MCFFEC */
  40
  41 #define CONFIG_HOSTNAME         "M5272C3"
  42 #define CONFIG_EXTRA_ENV_SETTINGS               \
  43         "netdev=eth0\0"                         \
  44         "loadaddr=10000\0"                      \
  45         "u-boot=u-boot.bin\0"                   \
  46         "load=tftp ${loadaddr) ${u-boot}\0"     \
  47         "upd=run load; run prog\0"              \
  48         "prog=prot off ffe00000 ffe3ffff;"      \
  49         "era ffe00000 ffe3ffff;"                \
  50         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  51         "save\0"                                \
  52         ""
  53
  54 #define CFG_SYS_CLK                     66000000
  55
  56 /*
  57  * Low Level Configuration Settings
  58  * (address mappings, register initial values, etc.)
  59  * You should know what you are doing if you make changes here.
  60  */
  61 #define CFG_SYS_MBAR            0x10000000      /* Register Base Addrs */
  62 #define CFG_SYS_SCR                     0x0003
  63 #define CFG_SYS_SPR                     0xffff
  64
  65 /*-----------------------------------------------------------------------
  66  * Definitions for initial stack pointer and data area (in DPRAM)
  67  */
  68 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  69 #define CFG_SYS_INIT_RAM_SIZE   0x1000  /* Size of used area in internal SRAM    */
  70
  71 /*-----------------------------------------------------------------------
  72  * Start addresses for the final memory configuration
  73  * (Set up by the startup code)
  74  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  75  */
  76 #define CFG_SYS_SDRAM_BASE              0x00000000
  77 #define CFG_SYS_SDRAM_SIZE              4       /* SDRAM size in MB */
  78 #define CFG_SYS_FLASH_BASE              0xffe00000
  79
  80 /*
  81  * For booting Linux, the board info and command line data
  82  * have to be in the first 8 MB of memory, since this is
  83  * the maximum mapped by the Linux kernel during initialization ??
  84  */
  85 #define CFG_SYS_BOOTMAPSZ               (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  86
  87 /*
  88  * FLASH organization
  89  */
  90 #ifdef CONFIG_SYS_FLASH_CFI
  91 #       define CFG_SYS_FLASH_SIZE               0x800000        /* Max size that the board might have */
  92 #endif
  93
  94 /*-----------------------------------------------------------------------
  95  * Cache Configuration
  96  */
  97
  98 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  99                                          CFG_SYS_INIT_RAM_SIZE - 8)
 100 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 101                                          CFG_SYS_INIT_RAM_SIZE - 4)
 102 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINV | CF_CACR_INVI)
 103 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
 104                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 105                                          CF_ACR_EN | CF_ACR_SM_ALL)
 106 #define CFG_SYS_CACHE_ICACR             (CF_CACR_CENB | CF_CACR_CINV | \
 107                                          CF_CACR_DISD | CF_CACR_INVI | \
 108                                          CF_CACR_CEIB | CF_CACR_DCM | \
 109                                          CF_CACR_EUSP)
 110
 111 /*-----------------------------------------------------------------------
 112  * Port configuration
 113  */
 114 #define CFG_SYS_PACNT           0x00000000
 115 #define CFG_SYS_PADDR           0x0000
 116 #define CFG_SYS_PADAT           0x0000
 117 #define CFG_SYS_PBCNT           0x55554155      /* Ethernet/UART configuration */
 118 #define CFG_SYS_PBDDR           0x0000
 119 #define CFG_SYS_PBDAT           0x0000
 120 #define CFG_SYS_PDCNT           0x00000000
 121 #endif                          /* _M5272C3_H */