2 * Configuation settings for the Motorola MC5272C3 board.
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_BAUDRATE 115200
26 #undef CONFIG_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
29 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
31 /* Configuration for environment
32 * Environment is embedded in u-boot in the second sector of the flash
34 #ifndef CONFIG_MONITOR_IS_IN_RAM
35 #define CONFIG_ENV_OFFSET 0x4000
36 #define CONFIG_ENV_SECT_SIZE 0x2000
37 #define CONFIG_ENV_IS_IN_FLASH 1
39 #define CONFIG_ENV_ADDR 0xffe04000
40 #define CONFIG_ENV_SECT_SIZE 0x2000
41 #define CONFIG_ENV_IS_IN_FLASH 1
47 #define CONFIG_BOOTP_BOOTFILESIZE
48 #define CONFIG_BOOTP_BOOTPATH
49 #define CONFIG_BOOTP_GATEWAY
50 #define CONFIG_BOOTP_HOSTNAME
53 * Command line configuration.
55 #include <config_cmd_default.h>
57 #define CONFIG_CMD_CACHE
58 #define CONFIG_CMD_MII
59 #define CONFIG_CMD_NET
60 #define CONFIG_CMD_PING
61 #define CONFIG_CMD_MISC
62 #define CONFIG_CMD_ELF
63 #define CONFIG_CMD_FLASH
64 #define CONFIG_CMD_MEMORY
66 #undef CONFIG_CMD_LOADS
67 #undef CONFIG_CMD_LOADB
69 #define CONFIG_BOOTDELAY 5
73 # define CONFIG_MII_INIT 1
74 # define CONFIG_SYS_DISCOVER_PHY
75 # define CONFIG_SYS_RX_ETH_BUFFER 8
76 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
78 # define CONFIG_SYS_FEC0_PINMUX 0
79 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
80 # define MCFFEC_TOUT_LOOP 50000
81 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
82 # ifndef CONFIG_SYS_DISCOVER_PHY
83 # define FECDUPLEX FULL
84 # define FECSPEED _100BASET
86 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
87 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
89 # endif /* CONFIG_SYS_DISCOVER_PHY */
93 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
94 # define CONFIG_IPADDR 192.162.1.2
95 # define CONFIG_NETMASK 255.255.255.0
96 # define CONFIG_SERVERIP 192.162.1.1
97 # define CONFIG_GATEWAYIP 192.162.1.1
98 # define CONFIG_OVERWRITE_ETHADDR_ONCE
99 #endif /* CONFIG_MCFFEC */
101 #define CONFIG_HOSTNAME M5272C3
102 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "u-boot=u-boot.bin\0" \
106 "load=tftp ${loadaddr) ${u-boot}\0" \
107 "upd=run load; run prog\0" \
108 "prog=prot off ffe00000 ffe3ffff;" \
109 "era ffe00000 ffe3ffff;" \
110 "cp.b ${loadaddr} ffe00000 ${filesize};"\
114 #define CONFIG_SYS_PROMPT "-> "
115 #define CONFIG_SYS_LONGHELP /* undef to save memory */
117 #if defined(CONFIG_CMD_KGDB)
118 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
120 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
126 #define CONFIG_SYS_LOAD_ADDR 0x20000
127 #define CONFIG_SYS_MEMTEST_START 0x400
128 #define CONFIG_SYS_MEMTEST_END 0x380000
129 #define CONFIG_SYS_CLK 66000000
132 * Low Level Configuration Settings
133 * (address mappings, register initial values, etc.)
134 * You should know what you are doing if you make changes here.
136 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
137 #define CONFIG_SYS_SCR 0x0003
138 #define CONFIG_SYS_SPR 0xffff
140 /*-----------------------------------------------------------------------
141 * Definitions for initial stack pointer and data area (in DPRAM)
143 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
144 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
145 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
148 /*-----------------------------------------------------------------------
149 * Start addresses for the final memory configuration
150 * (Set up by the startup code)
151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
153 #define CONFIG_SYS_SDRAM_BASE 0x00000000
154 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
155 #define CONFIG_SYS_FLASH_BASE 0xffe00000
157 #ifdef CONFIG_MONITOR_IS_IN_RAM
158 #define CONFIG_SYS_MONITOR_BASE 0x20000
160 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
163 #define CONFIG_SYS_MONITOR_LEN 0x20000
164 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
165 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
168 * For booting Linux, the board info and command line data
169 * have to be in the first 8 MB of memory, since this is
170 * the maximum mapped by the Linux kernel during initialization ??
172 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
177 #define CONFIG_SYS_FLASH_CFI
178 #ifdef CONFIG_SYS_FLASH_CFI
179 # define CONFIG_FLASH_CFI_DRIVER 1
180 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
181 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
182 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
183 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
184 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
187 /*-----------------------------------------------------------------------
188 * Cache Configuration
190 #define CONFIG_SYS_CACHELINE_SIZE 16
192 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
193 CONFIG_SYS_INIT_RAM_SIZE - 8)
194 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
195 CONFIG_SYS_INIT_RAM_SIZE - 4)
196 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
197 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
198 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
199 CF_ACR_EN | CF_ACR_SM_ALL)
200 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
201 CF_CACR_DISD | CF_CACR_INVI | \
202 CF_CACR_CEIB | CF_CACR_DCM | \
205 /*-----------------------------------------------------------------------
206 * Memory bank definitions
208 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201
209 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014
210 #define CONFIG_SYS_BR1_PRELIM 0
211 #define CONFIG_SYS_OR1_PRELIM 0
212 #define CONFIG_SYS_BR2_PRELIM 0x30000001
213 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000
214 #define CONFIG_SYS_BR3_PRELIM 0
215 #define CONFIG_SYS_OR3_PRELIM 0
216 #define CONFIG_SYS_BR4_PRELIM 0
217 #define CONFIG_SYS_OR4_PRELIM 0
218 #define CONFIG_SYS_BR5_PRELIM 0
219 #define CONFIG_SYS_OR5_PRELIM 0
220 #define CONFIG_SYS_BR6_PRELIM 0
221 #define CONFIG_SYS_OR6_PRELIM 0
222 #define CONFIG_SYS_BR7_PRELIM 0x00000701
223 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
225 /*-----------------------------------------------------------------------
228 #define CONFIG_SYS_PACNT 0x00000000
229 #define CONFIG_SYS_PADDR 0x0000
230 #define CONFIG_SYS_PADAT 0x0000
231 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
232 #define CONFIG_SYS_PBDDR 0x0000
233 #define CONFIG_SYS_PBDAT 0x0000
234 #define CONFIG_SYS_PDCNT 0x00000000
235 #endif /* _M5272C3_H */