2 * Configuation settings for the Motorola MC5272C3 board.
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_BAUDRATE 115200
26 #undef CONFIG_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
29 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
31 /* Configuration for environment
32 * Environment is embedded in u-boot in the second sector of the flash
34 #ifndef CONFIG_MONITOR_IS_IN_RAM
35 #define CONFIG_ENV_OFFSET 0x4000
36 #define CONFIG_ENV_SECT_SIZE 0x2000
37 #define CONFIG_ENV_IS_IN_FLASH 1
39 #define CONFIG_ENV_ADDR 0xffe04000
40 #define CONFIG_ENV_SECT_SIZE 0x2000
41 #define CONFIG_ENV_IS_IN_FLASH 1
44 #define LDS_BOARD_TEXT \
45 . = DEFINED(env_offset) ? env_offset : .; \
46 common/env_embedded.o (.text);
51 #define CONFIG_BOOTP_BOOTFILESIZE
52 #define CONFIG_BOOTP_BOOTPATH
53 #define CONFIG_BOOTP_GATEWAY
54 #define CONFIG_BOOTP_HOSTNAME
57 * Command line configuration.
60 #define CONFIG_BOOTDELAY 5
64 # define CONFIG_MII_INIT 1
65 # define CONFIG_SYS_DISCOVER_PHY
66 # define CONFIG_SYS_RX_ETH_BUFFER 8
67 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
69 # define CONFIG_SYS_FEC0_PINMUX 0
70 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
71 # define MCFFEC_TOUT_LOOP 50000
72 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
73 # ifndef CONFIG_SYS_DISCOVER_PHY
74 # define FECDUPLEX FULL
75 # define FECSPEED _100BASET
77 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
78 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
80 # endif /* CONFIG_SYS_DISCOVER_PHY */
84 # define CONFIG_IPADDR 192.162.1.2
85 # define CONFIG_NETMASK 255.255.255.0
86 # define CONFIG_SERVERIP 192.162.1.1
87 # define CONFIG_GATEWAYIP 192.162.1.1
88 #endif /* CONFIG_MCFFEC */
90 #define CONFIG_HOSTNAME M5272C3
91 #define CONFIG_EXTRA_ENV_SETTINGS \
94 "u-boot=u-boot.bin\0" \
95 "load=tftp ${loadaddr) ${u-boot}\0" \
96 "upd=run load; run prog\0" \
97 "prog=prot off ffe00000 ffe3ffff;" \
98 "era ffe00000 ffe3ffff;" \
99 "cp.b ${loadaddr} ffe00000 ${filesize};"\
103 #define CONFIG_SYS_LONGHELP /* undef to save memory */
105 #if defined(CONFIG_CMD_KGDB)
106 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
112 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
113 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
114 #define CONFIG_SYS_LOAD_ADDR 0x20000
115 #define CONFIG_SYS_MEMTEST_START 0x400
116 #define CONFIG_SYS_MEMTEST_END 0x380000
117 #define CONFIG_SYS_CLK 66000000
120 * Low Level Configuration Settings
121 * (address mappings, register initial values, etc.)
122 * You should know what you are doing if you make changes here.
124 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
125 #define CONFIG_SYS_SCR 0x0003
126 #define CONFIG_SYS_SPR 0xffff
128 /*-----------------------------------------------------------------------
129 * Definitions for initial stack pointer and data area (in DPRAM)
131 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
132 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
136 /*-----------------------------------------------------------------------
137 * Start addresses for the final memory configuration
138 * (Set up by the startup code)
139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
141 #define CONFIG_SYS_SDRAM_BASE 0x00000000
142 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
143 #define CONFIG_SYS_FLASH_BASE 0xffe00000
145 #ifdef CONFIG_MONITOR_IS_IN_RAM
146 #define CONFIG_SYS_MONITOR_BASE 0x20000
148 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
151 #define CONFIG_SYS_MONITOR_LEN 0x20000
152 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
153 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
156 * For booting Linux, the board info and command line data
157 * have to be in the first 8 MB of memory, since this is
158 * the maximum mapped by the Linux kernel during initialization ??
160 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
165 #define CONFIG_SYS_FLASH_CFI
166 #ifdef CONFIG_SYS_FLASH_CFI
167 # define CONFIG_FLASH_CFI_DRIVER 1
168 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
169 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
170 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
171 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
172 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
175 /*-----------------------------------------------------------------------
176 * Cache Configuration
178 #define CONFIG_SYS_CACHELINE_SIZE 16
180 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
181 CONFIG_SYS_INIT_RAM_SIZE - 8)
182 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
183 CONFIG_SYS_INIT_RAM_SIZE - 4)
184 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
185 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
186 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
187 CF_ACR_EN | CF_ACR_SM_ALL)
188 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
189 CF_CACR_DISD | CF_CACR_INVI | \
190 CF_CACR_CEIB | CF_CACR_DCM | \
193 /*-----------------------------------------------------------------------
194 * Memory bank definitions
196 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201
197 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014
198 #define CONFIG_SYS_BR1_PRELIM 0
199 #define CONFIG_SYS_OR1_PRELIM 0
200 #define CONFIG_SYS_BR2_PRELIM 0x30000001
201 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000
202 #define CONFIG_SYS_BR3_PRELIM 0
203 #define CONFIG_SYS_OR3_PRELIM 0
204 #define CONFIG_SYS_BR4_PRELIM 0
205 #define CONFIG_SYS_OR4_PRELIM 0
206 #define CONFIG_SYS_BR5_PRELIM 0
207 #define CONFIG_SYS_OR5_PRELIM 0
208 #define CONFIG_SYS_BR6_PRELIM 0
209 #define CONFIG_SYS_OR6_PRELIM 0
210 #define CONFIG_SYS_BR7_PRELIM 0x00000701
211 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
213 /*-----------------------------------------------------------------------
216 #define CONFIG_SYS_PACNT 0x00000000
217 #define CONFIG_SYS_PADDR 0x0000
218 #define CONFIG_SYS_PADAT 0x0000
219 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
220 #define CONFIG_SYS_PBDDR 0x0000
221 #define CONFIG_SYS_PBDAT 0x0000
222 #define CONFIG_SYS_PDCNT 0x00000000
223 #endif /* _M5272C3_H */