1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
9 #include <linux/stringify.h>
13 #define CONFIG_SYS_UART_PORT (0)
16 /* Configuration for environment
17 * Environment is embedded in u-boot in the second sector of the flash
20 #define LDS_BOARD_TEXT \
21 . = DEFINED(env_offset) ? env_offset : .; \
22 env/embedded.o(.text*);
26 # define CONFIG_IDE_RESET 1
27 # define CONFIG_IDE_PREINIT 1
31 # define CONFIG_SYS_IDE_MAXBUS 1
32 # define CONFIG_SYS_IDE_MAXDEVICE 2
34 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
35 # define CONFIG_SYS_ATA_IDE0_OFFSET 0
37 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
38 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
39 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
40 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
43 #define CONFIG_DRIVER_DM9000
44 #ifdef CONFIG_DRIVER_DM9000
45 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
46 # define DM9000_IO CONFIG_DM9000_BASE
47 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
48 # undef CONFIG_DM9000_DEBUG
49 # define CONFIG_DM9000_BYTE_SWAPPED
51 # define CONFIG_OVERWRITE_ETHADDR_ONCE
53 # define CONFIG_EXTRA_ENV_SETTINGS \
55 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
57 "u-boot=u-boot.bin\0" \
58 "load=tftp ${loadaddr) ${u-boot}\0" \
59 "upd=run load; run prog\0" \
60 "prog=prot off 0xff800000 0xff82ffff;" \
61 "era 0xff800000 0xff82ffff;" \
62 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
67 #define CONFIG_HOSTNAME "M5253DEMO"
70 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
71 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
72 #define CONFIG_SYS_I2C_PINMUX_SET (0)
74 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
75 #define CONFIG_SYS_FAST_CLK
76 #ifdef CONFIG_SYS_FAST_CLK
77 # define CONFIG_SYS_PLLCR 0x1243E054
78 # define CONFIG_SYS_CLK 140000000
80 # define CONFIG_SYS_PLLCR 0x135a4140
81 # define CONFIG_SYS_CLK 70000000
85 * Low Level Configuration Settings
86 * (address mappings, register initial values, etc.)
87 * You should know what you are doing if you make changes here.
90 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
91 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
94 * Definitions for initial stack pointer and data area (in DPRAM)
96 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
97 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
98 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
99 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
102 * Start addresses for the final memory configuration
103 * (Set up by the startup code)
104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
106 #define CONFIG_SYS_SDRAM_BASE 0x00000000
107 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
109 #ifdef CONFIG_MONITOR_IS_IN_RAM
110 # define CONFIG_SYS_MONITOR_BASE 0x20000
112 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
115 #define CONFIG_SYS_MONITOR_LEN 0x40000
116 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
119 * For booting Linux, the board info and command line data
120 * have to be in the first 8 MB of memory, since this is
121 * the maximum mapped by the Linux kernel during initialization ??
123 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
124 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
126 /* FLASH organization */
127 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
128 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
129 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
130 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
132 #define FLASH_SST6401B 0x200
133 #define SST_ID_xF6401B 0x236D236D
135 #ifdef CONFIG_SYS_FLASH_CFI
137 * Unable to use CFI driver, due to incompatible sector erase command by SST.
138 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
139 * 0x30 is block erase in SST
141 # define CONFIG_SYS_FLASH_SIZE 0x800000
142 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
143 # define CONFIG_FLASH_CFI_LEGACY
145 # define CONFIG_SYS_SST_SECT 2048
146 # define CONFIG_SYS_SST_SECTSZ 0x1000
147 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
150 /* Cache Configuration */
152 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
153 CONFIG_SYS_INIT_RAM_SIZE - 8)
154 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
155 CONFIG_SYS_INIT_RAM_SIZE - 4)
156 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
157 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
159 CF_ACR_EN | CF_ACR_SM_ALL)
160 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
161 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
162 CF_ACR_EN | CF_ACR_SM_ALL)
163 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
166 /* Port configuration */
167 #define CONFIG_SYS_FECI2C 0xF0
169 #define CONFIG_SYS_CS0_BASE 0xFF800000
170 #define CONFIG_SYS_CS0_MASK 0x007F0021
171 #define CONFIG_SYS_CS0_CTRL 0x00001D80
173 #define CONFIG_SYS_CS1_BASE 0xE0000000
174 #define CONFIG_SYS_CS1_MASK 0x00000001
175 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
177 /*-----------------------------------------------------------------------
180 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
181 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
182 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
183 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
184 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
185 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
186 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
188 #endif /* _M5253DEMO_H */