1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
9 #include <linux/stringify.h>
13 #define CONFIG_MCFUART
14 #define CONFIG_SYS_UART_PORT (0)
16 #undef CONFIG_WATCHDOG /* disable watchdog */
19 /* Configuration for environment
20 * Environment is embedded in u-boot in the second sector of the flash
23 #define LDS_BOARD_TEXT \
24 . = DEFINED(env_offset) ? env_offset : .; \
25 env/embedded.o(.text*);
28 * Command line configuration.
33 # define CONFIG_IDE_RESET 1
34 # define CONFIG_IDE_PREINIT 1
38 # define CONFIG_SYS_IDE_MAXBUS 1
39 # define CONFIG_SYS_IDE_MAXDEVICE 2
41 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
42 # define CONFIG_SYS_ATA_IDE0_OFFSET 0
44 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
45 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
46 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
47 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
50 #define CONFIG_DRIVER_DM9000
51 #ifdef CONFIG_DRIVER_DM9000
52 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
53 # define DM9000_IO CONFIG_DM9000_BASE
54 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
55 # undef CONFIG_DM9000_DEBUG
56 # define CONFIG_DM9000_BYTE_SWAPPED
58 # define CONFIG_OVERWRITE_ETHADDR_ONCE
60 # define CONFIG_EXTRA_ENV_SETTINGS \
62 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
64 "u-boot=u-boot.bin\0" \
65 "load=tftp ${loadaddr) ${u-boot}\0" \
66 "upd=run load; run prog\0" \
67 "prog=prot off 0xff800000 0xff82ffff;" \
68 "era 0xff800000 0xff82ffff;" \
69 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
74 #define CONFIG_HOSTNAME "M5253DEMO"
77 #define CONFIG_SYS_I2C
78 #define CONFIG_SYS_I2C_FSL
79 #define CONFIG_SYS_FSL_I2C_SPEED 80000
80 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
81 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
82 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
83 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
84 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
85 #define CONFIG_SYS_I2C_PINMUX_SET (0)
87 #define CONFIG_SYS_LOAD_ADDR 0x00100000
89 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
90 #define CONFIG_SYS_FAST_CLK
91 #ifdef CONFIG_SYS_FAST_CLK
92 # define CONFIG_SYS_PLLCR 0x1243E054
93 # define CONFIG_SYS_CLK 140000000
95 # define CONFIG_SYS_PLLCR 0x135a4140
96 # define CONFIG_SYS_CLK 70000000
100 * Low Level Configuration Settings
101 * (address mappings, register initial values, etc.)
102 * You should know what you are doing if you make changes here.
105 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
106 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
109 * Definitions for initial stack pointer and data area (in DPRAM)
111 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
112 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
113 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
114 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
117 * Start addresses for the final memory configuration
118 * (Set up by the startup code)
119 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
121 #define CONFIG_SYS_SDRAM_BASE 0x00000000
122 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
124 #ifdef CONFIG_MONITOR_IS_IN_RAM
125 # define CONFIG_SYS_MONITOR_BASE 0x20000
127 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
130 #define CONFIG_SYS_MONITOR_LEN 0x40000
131 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
132 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
135 * For booting Linux, the board info and command line data
136 * have to be in the first 8 MB of memory, since this is
137 * the maximum mapped by the Linux kernel during initialization ??
139 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
140 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
142 /* FLASH organization */
143 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
144 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
145 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
146 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
148 #define FLASH_SST6401B 0x200
149 #define SST_ID_xF6401B 0x236D236D
151 #ifdef CONFIG_SYS_FLASH_CFI
153 * Unable to use CFI driver, due to incompatible sector erase command by SST.
154 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
155 * 0x30 is block erase in SST
157 # define CONFIG_SYS_FLASH_SIZE 0x800000
158 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
159 # define CONFIG_FLASH_CFI_LEGACY
161 # define CONFIG_SYS_SST_SECT 2048
162 # define CONFIG_SYS_SST_SECTSZ 0x1000
163 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
166 /* Cache Configuration */
167 #define CONFIG_SYS_CACHELINE_SIZE 16
169 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
170 CONFIG_SYS_INIT_RAM_SIZE - 8)
171 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
172 CONFIG_SYS_INIT_RAM_SIZE - 4)
173 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
174 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
176 CF_ACR_EN | CF_ACR_SM_ALL)
177 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
178 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
179 CF_ACR_EN | CF_ACR_SM_ALL)
180 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
183 /* Port configuration */
184 #define CONFIG_SYS_FECI2C 0xF0
186 #define CONFIG_SYS_CS0_BASE 0xFF800000
187 #define CONFIG_SYS_CS0_MASK 0x007F0021
188 #define CONFIG_SYS_CS0_CTRL 0x00001D80
190 #define CONFIG_SYS_CS1_BASE 0xE0000000
191 #define CONFIG_SYS_CS1_MASK 0x00000001
192 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
194 /*-----------------------------------------------------------------------
197 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
198 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
199 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
200 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
201 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
202 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
203 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
205 #endif /* _M5253DEMO_H */