1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
9 #include <linux/stringify.h>
13 #define CONFIG_SYS_UART_PORT (0)
15 #undef CONFIG_WATCHDOG /* disable watchdog */
18 /* Configuration for environment
19 * Environment is embedded in u-boot in the second sector of the flash
22 #define LDS_BOARD_TEXT \
23 . = DEFINED(env_offset) ? env_offset : .; \
24 env/embedded.o(.text*);
28 # define CONFIG_IDE_RESET 1
29 # define CONFIG_IDE_PREINIT 1
33 # define CONFIG_SYS_IDE_MAXBUS 1
34 # define CONFIG_SYS_IDE_MAXDEVICE 2
36 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
37 # define CONFIG_SYS_ATA_IDE0_OFFSET 0
39 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
40 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
41 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
42 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
45 #define CONFIG_DRIVER_DM9000
46 #ifdef CONFIG_DRIVER_DM9000
47 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
48 # define DM9000_IO CONFIG_DM9000_BASE
49 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
50 # undef CONFIG_DM9000_DEBUG
51 # define CONFIG_DM9000_BYTE_SWAPPED
53 # define CONFIG_OVERWRITE_ETHADDR_ONCE
55 # define CONFIG_EXTRA_ENV_SETTINGS \
57 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
59 "u-boot=u-boot.bin\0" \
60 "load=tftp ${loadaddr) ${u-boot}\0" \
61 "upd=run load; run prog\0" \
62 "prog=prot off 0xff800000 0xff82ffff;" \
63 "era 0xff800000 0xff82ffff;" \
64 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
69 #define CONFIG_HOSTNAME "M5253DEMO"
72 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
73 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
74 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
75 #define CONFIG_SYS_I2C_PINMUX_SET (0)
77 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
78 #define CONFIG_SYS_FAST_CLK
79 #ifdef CONFIG_SYS_FAST_CLK
80 # define CONFIG_SYS_PLLCR 0x1243E054
81 # define CONFIG_SYS_CLK 140000000
83 # define CONFIG_SYS_PLLCR 0x135a4140
84 # define CONFIG_SYS_CLK 70000000
88 * Low Level Configuration Settings
89 * (address mappings, register initial values, etc.)
90 * You should know what you are doing if you make changes here.
93 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
94 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
97 * Definitions for initial stack pointer and data area (in DPRAM)
99 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
100 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
101 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
102 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105 * Start addresses for the final memory configuration
106 * (Set up by the startup code)
107 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
109 #define CONFIG_SYS_SDRAM_BASE 0x00000000
110 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
112 #ifdef CONFIG_MONITOR_IS_IN_RAM
113 # define CONFIG_SYS_MONITOR_BASE 0x20000
115 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
118 #define CONFIG_SYS_MONITOR_LEN 0x40000
119 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
122 * For booting Linux, the board info and command line data
123 * have to be in the first 8 MB of memory, since this is
124 * the maximum mapped by the Linux kernel during initialization ??
126 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
127 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
129 /* FLASH organization */
130 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
133 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
135 #define FLASH_SST6401B 0x200
136 #define SST_ID_xF6401B 0x236D236D
138 #ifdef CONFIG_SYS_FLASH_CFI
140 * Unable to use CFI driver, due to incompatible sector erase command by SST.
141 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
142 * 0x30 is block erase in SST
144 # define CONFIG_SYS_FLASH_SIZE 0x800000
145 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
146 # define CONFIG_FLASH_CFI_LEGACY
148 # define CONFIG_SYS_SST_SECT 2048
149 # define CONFIG_SYS_SST_SECTSZ 0x1000
150 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
153 /* Cache Configuration */
155 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
156 CONFIG_SYS_INIT_RAM_SIZE - 8)
157 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
158 CONFIG_SYS_INIT_RAM_SIZE - 4)
159 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
160 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
162 CF_ACR_EN | CF_ACR_SM_ALL)
163 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
164 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
165 CF_ACR_EN | CF_ACR_SM_ALL)
166 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
169 /* Port configuration */
170 #define CONFIG_SYS_FECI2C 0xF0
172 #define CONFIG_SYS_CS0_BASE 0xFF800000
173 #define CONFIG_SYS_CS0_MASK 0x007F0021
174 #define CONFIG_SYS_CS0_CTRL 0x00001D80
176 #define CONFIG_SYS_CS1_BASE 0xE0000000
177 #define CONFIG_SYS_CS1_MASK 0x00000001
178 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
180 /*-----------------------------------------------------------------------
183 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
184 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
185 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
186 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
187 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
188 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
189 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
191 #endif /* _M5253DEMO_H */