1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
9 #include <linux/stringify.h>
13 #define CONFIG_MCFUART
14 #define CONFIG_SYS_UART_PORT (0)
16 #undef CONFIG_WATCHDOG /* disable watchdog */
19 /* Configuration for environment
20 * Environment is embedded in u-boot in the second sector of the flash
23 #define LDS_BOARD_TEXT \
24 . = DEFINED(env_offset) ? env_offset : .; \
25 env/embedded.o(.text*);
29 # define CONFIG_IDE_RESET 1
30 # define CONFIG_IDE_PREINIT 1
34 # define CONFIG_SYS_IDE_MAXBUS 1
35 # define CONFIG_SYS_IDE_MAXDEVICE 2
37 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
38 # define CONFIG_SYS_ATA_IDE0_OFFSET 0
40 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
41 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
42 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
43 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
46 #define CONFIG_DRIVER_DM9000
47 #ifdef CONFIG_DRIVER_DM9000
48 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
49 # define DM9000_IO CONFIG_DM9000_BASE
50 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
51 # undef CONFIG_DM9000_DEBUG
52 # define CONFIG_DM9000_BYTE_SWAPPED
54 # define CONFIG_OVERWRITE_ETHADDR_ONCE
56 # define CONFIG_EXTRA_ENV_SETTINGS \
58 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
60 "u-boot=u-boot.bin\0" \
61 "load=tftp ${loadaddr) ${u-boot}\0" \
62 "upd=run load; run prog\0" \
63 "prog=prot off 0xff800000 0xff82ffff;" \
64 "era 0xff800000 0xff82ffff;" \
65 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
70 #define CONFIG_HOSTNAME "M5253DEMO"
73 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
74 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
75 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
76 #define CONFIG_SYS_I2C_PINMUX_SET (0)
78 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
79 #define CONFIG_SYS_FAST_CLK
80 #ifdef CONFIG_SYS_FAST_CLK
81 # define CONFIG_SYS_PLLCR 0x1243E054
82 # define CONFIG_SYS_CLK 140000000
84 # define CONFIG_SYS_PLLCR 0x135a4140
85 # define CONFIG_SYS_CLK 70000000
89 * Low Level Configuration Settings
90 * (address mappings, register initial values, etc.)
91 * You should know what you are doing if you make changes here.
94 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
95 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
98 * Definitions for initial stack pointer and data area (in DPRAM)
100 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
101 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
102 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106 * Start addresses for the final memory configuration
107 * (Set up by the startup code)
108 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
110 #define CONFIG_SYS_SDRAM_BASE 0x00000000
111 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
113 #ifdef CONFIG_MONITOR_IS_IN_RAM
114 # define CONFIG_SYS_MONITOR_BASE 0x20000
116 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
119 #define CONFIG_SYS_MONITOR_LEN 0x40000
120 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
123 * For booting Linux, the board info and command line data
124 * have to be in the first 8 MB of memory, since this is
125 * the maximum mapped by the Linux kernel during initialization ??
127 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
128 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
130 /* FLASH organization */
131 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
132 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
133 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
134 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
136 #define FLASH_SST6401B 0x200
137 #define SST_ID_xF6401B 0x236D236D
139 #ifdef CONFIG_SYS_FLASH_CFI
141 * Unable to use CFI driver, due to incompatible sector erase command by SST.
142 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
143 * 0x30 is block erase in SST
145 # define CONFIG_SYS_FLASH_SIZE 0x800000
146 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
147 # define CONFIG_FLASH_CFI_LEGACY
149 # define CONFIG_SYS_SST_SECT 2048
150 # define CONFIG_SYS_SST_SECTSZ 0x1000
151 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
154 /* Cache Configuration */
156 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
157 CONFIG_SYS_INIT_RAM_SIZE - 8)
158 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
159 CONFIG_SYS_INIT_RAM_SIZE - 4)
160 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
161 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
163 CF_ACR_EN | CF_ACR_SM_ALL)
164 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
165 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
166 CF_ACR_EN | CF_ACR_SM_ALL)
167 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
170 /* Port configuration */
171 #define CONFIG_SYS_FECI2C 0xF0
173 #define CONFIG_SYS_CS0_BASE 0xFF800000
174 #define CONFIG_SYS_CS0_MASK 0x007F0021
175 #define CONFIG_SYS_CS0_CTRL 0x00001D80
177 #define CONFIG_SYS_CS1_BASE 0xE0000000
178 #define CONFIG_SYS_CS1_MASK 0x00000001
179 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
181 /*-----------------------------------------------------------------------
184 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
185 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
186 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
187 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
188 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
189 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
190 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
192 #endif /* _M5253DEMO_H */