1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
9 #include <linux/stringify.h>
11 #define CONFIG_SYS_UART_PORT (0)
14 /* Configuration for environment
15 * Environment is embedded in u-boot in the second sector of the flash
18 #define LDS_BOARD_TEXT \
19 . = DEFINED(env_offset) ? env_offset : .; \
20 env/embedded.o(.text*);
22 #ifdef CONFIG_DRIVER_DM9000
23 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
24 # define DM9000_IO CONFIG_DM9000_BASE
25 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
26 # undef CONFIG_DM9000_DEBUG
27 # define CONFIG_DM9000_BYTE_SWAPPED
29 # define CONFIG_OVERWRITE_ETHADDR_ONCE
31 # define CONFIG_EXTRA_ENV_SETTINGS \
33 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
35 "u-boot=u-boot.bin\0" \
36 "load=tftp ${loadaddr) ${u-boot}\0" \
37 "upd=run load; run prog\0" \
38 "prog=prot off 0xff800000 0xff82ffff;" \
39 "era 0xff800000 0xff82ffff;" \
40 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
45 #define CONFIG_HOSTNAME "M5253DEMO"
48 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
49 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
50 #define CONFIG_SYS_I2C_PINMUX_SET (0)
52 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
53 #define CONFIG_SYS_FAST_CLK
54 #ifdef CONFIG_SYS_FAST_CLK
55 # define CONFIG_SYS_PLLCR 0x1243E054
56 # define CONFIG_SYS_CLK 140000000
58 # define CONFIG_SYS_PLLCR 0x135a4140
59 # define CONFIG_SYS_CLK 70000000
63 * Low Level Configuration Settings
64 * (address mappings, register initial values, etc.)
65 * You should know what you are doing if you make changes here.
68 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
69 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
72 * Definitions for initial stack pointer and data area (in DPRAM)
74 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
75 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
78 * Start addresses for the final memory configuration
79 * (Set up by the startup code)
80 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
82 #define CONFIG_SYS_SDRAM_BASE 0x00000000
83 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
85 #define CONFIG_SYS_MONITOR_LEN 0x40000
88 * For booting Linux, the board info and command line data
89 * have to be in the first 8 MB of memory, since this is
90 * the maximum mapped by the Linux kernel during initialization ??
92 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
94 /* FLASH organization */
95 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
97 #define FLASH_SST6401B 0x200
98 #define SST_ID_xF6401B 0x236D236D
100 #ifdef CONFIG_SYS_FLASH_CFI
102 * Unable to use CFI driver, due to incompatible sector erase command by SST.
103 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
104 * 0x30 is block erase in SST
106 # define CONFIG_SYS_FLASH_SIZE 0x800000
108 # define CONFIG_SYS_SST_SECT 2048
109 # define CONFIG_SYS_SST_SECTSZ 0x1000
112 /* Cache Configuration */
114 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
115 CONFIG_SYS_INIT_RAM_SIZE - 8)
116 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
117 CONFIG_SYS_INIT_RAM_SIZE - 4)
118 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
119 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
121 CF_ACR_EN | CF_ACR_SM_ALL)
122 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
123 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
124 CF_ACR_EN | CF_ACR_SM_ALL)
125 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
128 #define CONFIG_SYS_CS0_BASE 0xFF800000
129 #define CONFIG_SYS_CS0_MASK 0x007F0021
130 #define CONFIG_SYS_CS0_CTRL 0x00001D80
132 #define CONFIG_SYS_CS1_BASE 0xE0000000
133 #define CONFIG_SYS_CS1_MASK 0x00000001
134 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
136 /*-----------------------------------------------------------------------
139 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
140 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
141 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
142 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
143 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
144 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
145 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
147 #endif /* _M5253DEMO_H */