1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
11 #define CONFIG_MCFUART
12 #define CONFIG_SYS_UART_PORT (0)
14 #undef CONFIG_WATCHDOG /* disable watchdog */
17 /* Configuration for environment
18 * Environment is embedded in u-boot in the second sector of the flash
20 #ifdef CONFIG_MONITOR_IS_IN_RAM
21 # define CONFIG_ENV_OFFSET 0x4000
22 # define CONFIG_ENV_SECT_SIZE 0x1000
24 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
25 # define CONFIG_ENV_SECT_SIZE 0x1000
28 #define LDS_BOARD_TEXT \
29 . = DEFINED(env_offset) ? env_offset : .; \
30 env/embedded.o(.text*);
33 * Command line configuration.
38 # define CONFIG_IDE_RESET 1
39 # define CONFIG_IDE_PREINIT 1
43 # define CONFIG_SYS_IDE_MAXBUS 1
44 # define CONFIG_SYS_IDE_MAXDEVICE 2
46 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
47 # define CONFIG_SYS_ATA_IDE0_OFFSET 0
49 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
50 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
51 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
52 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
55 #define CONFIG_DRIVER_DM9000
56 #ifdef CONFIG_DRIVER_DM9000
57 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
58 # define DM9000_IO CONFIG_DM9000_BASE
59 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
60 # undef CONFIG_DM9000_DEBUG
61 # define CONFIG_DM9000_BYTE_SWAPPED
63 # define CONFIG_OVERWRITE_ETHADDR_ONCE
65 # define CONFIG_EXTRA_ENV_SETTINGS \
67 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
69 "u-boot=u-boot.bin\0" \
70 "load=tftp ${loadaddr) ${u-boot}\0" \
71 "upd=run load; run prog\0" \
72 "prog=prot off 0xff800000 0xff82ffff;" \
73 "era 0xff800000 0xff82ffff;" \
74 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
79 #define CONFIG_HOSTNAME "M5253DEMO"
82 #define CONFIG_SYS_I2C
83 #define CONFIG_SYS_I2C_FSL
84 #define CONFIG_SYS_FSL_I2C_SPEED 80000
85 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
86 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
87 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
88 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
89 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
90 #define CONFIG_SYS_I2C_PINMUX_SET (0)
92 #define CONFIG_SYS_LOAD_ADDR 0x00100000
94 #define CONFIG_SYS_MEMTEST_START 0x400
95 #define CONFIG_SYS_MEMTEST_END 0x380000
97 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
98 #define CONFIG_SYS_FAST_CLK
99 #ifdef CONFIG_SYS_FAST_CLK
100 # define CONFIG_SYS_PLLCR 0x1243E054
101 # define CONFIG_SYS_CLK 140000000
103 # define CONFIG_SYS_PLLCR 0x135a4140
104 # define CONFIG_SYS_CLK 70000000
108 * Low Level Configuration Settings
109 * (address mappings, register initial values, etc.)
110 * You should know what you are doing if you make changes here.
113 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
114 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
117 * Definitions for initial stack pointer and data area (in DPRAM)
119 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
120 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
121 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
122 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
125 * Start addresses for the final memory configuration
126 * (Set up by the startup code)
127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
129 #define CONFIG_SYS_SDRAM_BASE 0x00000000
130 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
132 #ifdef CONFIG_MONITOR_IS_IN_RAM
133 # define CONFIG_SYS_MONITOR_BASE 0x20000
135 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
138 #define CONFIG_SYS_MONITOR_LEN 0x40000
139 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
140 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
143 * For booting Linux, the board info and command line data
144 * have to be in the first 8 MB of memory, since this is
145 * the maximum mapped by the Linux kernel during initialization ??
147 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
148 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
150 /* FLASH organization */
151 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
153 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
154 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
156 #define FLASH_SST6401B 0x200
157 #define SST_ID_xF6401B 0x236D236D
159 #ifdef CONFIG_SYS_FLASH_CFI
161 * Unable to use CFI driver, due to incompatible sector erase command by SST.
162 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
163 * 0x30 is block erase in SST
165 # define CONFIG_SYS_FLASH_SIZE 0x800000
166 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
167 # define CONFIG_FLASH_CFI_LEGACY
169 # define CONFIG_SYS_SST_SECT 2048
170 # define CONFIG_SYS_SST_SECTSZ 0x1000
171 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
174 /* Cache Configuration */
175 #define CONFIG_SYS_CACHELINE_SIZE 16
177 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
178 CONFIG_SYS_INIT_RAM_SIZE - 8)
179 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
180 CONFIG_SYS_INIT_RAM_SIZE - 4)
181 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
182 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
184 CF_ACR_EN | CF_ACR_SM_ALL)
185 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
186 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
187 CF_ACR_EN | CF_ACR_SM_ALL)
188 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
191 /* Port configuration */
192 #define CONFIG_SYS_FECI2C 0xF0
194 #define CONFIG_SYS_CS0_BASE 0xFF800000
195 #define CONFIG_SYS_CS0_MASK 0x007F0021
196 #define CONFIG_SYS_CS0_CTRL 0x00001D80
198 #define CONFIG_SYS_CS1_BASE 0xE0000000
199 #define CONFIG_SYS_CS1_MASK 0x00000001
200 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
202 /*-----------------------------------------------------------------------
205 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
206 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
207 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
208 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
209 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
210 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
211 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
213 #endif /* _M5253DEMO_H */