1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the esd TASREG board.
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
26 * Clock configuration: enable only one of the following options
29 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
30 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
31 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
34 * Low Level Configuration Settings
35 * (address mappings, register initial values, etc.)
36 * You should know what you are doing if you make changes here.
39 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
40 #define CONFIG_SYS_MBAR2 0x80000000
42 /*-----------------------------------------------------------------------
43 * Definitions for initial stack pointer and data area (in DPRAM)
45 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
46 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
47 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
48 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
50 #define LDS_BOARD_TEXT \
51 . = DEFINED(env_offset) ? env_offset : .; \
52 env/embedded.o(.text);
54 /*-----------------------------------------------------------------------
55 * Start addresses for the final memory configuration
56 * (Set up by the startup code)
57 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
59 #define CONFIG_SYS_SDRAM_BASE 0x00000000
60 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
61 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
64 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
67 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
69 #define CONFIG_SYS_MONITOR_LEN 0x20000
70 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
73 * For booting Linux, the board info and command line data
74 * have to be in the first 8 MB of memory, since this is
75 * the maximum mapped by the Linux kernel during initialization ??
77 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
79 /*-----------------------------------------------------------------------
82 #ifdef CONFIG_SYS_FLASH_CFI
84 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
85 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
86 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
87 # define CONFIG_SYS_FLASH_CHECKSUM
88 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
91 /*-----------------------------------------------------------------------
95 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
96 CONFIG_SYS_INIT_RAM_SIZE - 8)
97 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
98 CONFIG_SYS_INIT_RAM_SIZE - 4)
99 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
100 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
102 CF_ACR_EN | CF_ACR_SM_ALL)
103 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
104 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
105 CF_ACR_EN | CF_ACR_SM_ALL)
106 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
109 /*-----------------------------------------------------------------------
110 * Memory bank definitions
113 /* CS0 - AMD Flash, address 0xffc00000 */
114 #define CONFIG_SYS_CS0_BASE 0xffe00000
115 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
116 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
117 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
119 /* CS1 - FPGA, address 0xe0000000 */
120 #define CONFIG_SYS_CS1_BASE 0xe0000000
121 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
122 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
124 /*-----------------------------------------------------------------------
127 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
128 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
129 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
130 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
131 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
132 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
133 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */