1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the esd TASREG board.
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
27 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
32 #undef CONFIG_BOOTP_BOOTFILESIZE
34 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
36 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
39 * Clock configuration: enable only one of the following options
42 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
43 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
44 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
47 * Low Level Configuration Settings
48 * (address mappings, register initial values, etc.)
49 * You should know what you are doing if you make changes here.
52 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
53 #define CONFIG_SYS_MBAR2 0x80000000
55 /*-----------------------------------------------------------------------
56 * Definitions for initial stack pointer and data area (in DPRAM)
58 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
59 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
60 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
61 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
63 #define LDS_BOARD_TEXT \
64 . = DEFINED(env_offset) ? env_offset : .; \
65 env/embedded.o(.text);
67 /*-----------------------------------------------------------------------
68 * Start addresses for the final memory configuration
69 * (Set up by the startup code)
70 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
72 #define CONFIG_SYS_SDRAM_BASE 0x00000000
73 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
74 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
77 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
80 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
82 #define CONFIG_SYS_MONITOR_LEN 0x20000
83 #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
84 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
87 * For booting Linux, the board info and command line data
88 * have to be in the first 8 MB of memory, since this is
89 * the maximum mapped by the Linux kernel during initialization ??
91 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
93 /*-----------------------------------------------------------------------
96 #ifdef CONFIG_SYS_FLASH_CFI
98 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
99 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
100 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
101 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
102 # define CONFIG_SYS_FLASH_CHECKSUM
103 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
106 /*-----------------------------------------------------------------------
107 * Cache Configuration
109 #define CONFIG_SYS_CACHELINE_SIZE 16
111 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
112 CONFIG_SYS_INIT_RAM_SIZE - 8)
113 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
114 CONFIG_SYS_INIT_RAM_SIZE - 4)
115 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
116 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
118 CF_ACR_EN | CF_ACR_SM_ALL)
119 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
120 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
121 CF_ACR_EN | CF_ACR_SM_ALL)
122 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
125 /*-----------------------------------------------------------------------
126 * Memory bank definitions
129 /* CS0 - AMD Flash, address 0xffc00000 */
130 #define CONFIG_SYS_CS0_BASE 0xffe00000
131 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
132 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
133 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
135 /* CS1 - FPGA, address 0xe0000000 */
136 #define CONFIG_SYS_CS1_BASE 0xe0000000
137 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
138 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
140 /*-----------------------------------------------------------------------
143 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
144 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
145 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
146 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
147 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
148 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
149 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */