include/configs/M5249EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the esd TASREG board.
   4  *
   5  * (C) Copyright 2004
   6  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5249EVB_H
  14 #define _M5249EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #undef CONFIG_MONITOR_IS_IN_RAM         /* no pre-loader required!!! ;-) */
  24
  25 /*
  26  * Clock configuration: enable only one of the following options
  27  */
  28
  29 #undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
  30 #define CONFIG_SYS_FAST_CLK             1               /* MCF5249 can run at 140MHz   */
  31 #define CONFIG_SYS_CLK                  132025600       /* MCF5249 can run at 140MHz   */
  32
  33 /*
  34  * Low Level Configuration Settings
  35  * (address mappings, register initial values, etc.)
  36  * You should know what you are doing if you make changes here.
  37  */
  38
  39 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
  40 #define CONFIG_SYS_MBAR2                0x80000000
  41
  42 /*-----------------------------------------------------------------------
  43  * Definitions for initial stack pointer and data area (in DPRAM)
  44  */
  45 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  46 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM   */
  47 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  48
  49 #define LDS_BOARD_TEXT \
  50         . = DEFINED(env_offset) ? env_offset : .; \
  51         env/embedded.o(.text);
  52
  53 /*-----------------------------------------------------------------------
  54  * Start addresses for the final memory configuration
  55  * (Set up by the startup code)
  56  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  57  */
  58 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  59 #define CONFIG_SYS_SDRAM_SIZE           16              /* SDRAM size in MB */
  60 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
  61
  62 #if 0 /* test-only */
  63 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
  64 #endif
  65
  66 #define CONFIG_SYS_MONITOR_LEN          0x20000
  67
  68 /*
  69  * For booting Linux, the board info and command line data
  70  * have to be in the first 8 MB of memory, since this is
  71  * the maximum mapped by the Linux kernel during initialization ??
  72  */
  73 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  74
  75 /*-----------------------------------------------------------------------
  76  * FLASH organization
  77  */
  78 #ifdef CONFIG_SYS_FLASH_CFI
  79
  80 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
  81 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
  82 #       define CONFIG_SYS_FLASH_CHECKSUM
  83 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
  84 #endif
  85
  86 /*-----------------------------------------------------------------------
  87  * Cache Configuration
  88  */
  89
  90 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  91                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
  92 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  93                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
  94 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
  95 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
  96                                          CF_ADDRMASK(2) | \
  97                                          CF_ACR_EN | CF_ACR_SM_ALL)
  98 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
  99                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 100                                          CF_ACR_EN | CF_ACR_SM_ALL)
 101 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 102                                          CF_CACR_DBWE)
 103
 104 /*-----------------------------------------------------------------------
 105  * Memory bank definitions
 106  */
 107
 108 /* CS0 - AMD Flash, address 0xffc00000 */
 109 #define CONFIG_SYS_CS0_BASE             0xffe00000
 110 #define CONFIG_SYS_CS0_CTRL             0x00001980      /* WS=0110, AA=1, PS=10         */
 111 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
 112 #define CONFIG_SYS_CS0_MASK             0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
 113
 114 /* CS1 - FPGA, address 0xe0000000 */
 115 #define CONFIG_SYS_CS1_BASE             0xe0000000
 116 #define CONFIG_SYS_CS1_CTRL             0x00000d80      /* WS=0011, AA=1, PS=10         */
 117 #define CONFIG_SYS_CS1_MASK             0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
 118
 119 /*-----------------------------------------------------------------------
 120  * Port configuration
 121  */
 122 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none          */
 123 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
 124 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable       */
 125 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable       */
 126 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 127 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 128 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led                     */
 129
 130 #endif  /* M5249 */