1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
26 # define CONFIG_SYS_DISCOVER_PHY
27 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
28 # ifndef CONFIG_SYS_DISCOVER_PHY
29 # define FECDUPLEX FULL
30 # define FECSPEED _100BASET
31 # endif /* CONFIG_SYS_DISCOVER_PHY */
35 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
36 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
37 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
39 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
41 # define CONFIG_IPADDR 192.162.1.2
42 # define CONFIG_NETMASK 255.255.255.0
43 # define CONFIG_SERVERIP 192.162.1.1
44 # define CONFIG_GATEWAYIP 192.162.1.1
47 #define CONFIG_HOSTNAME "M5235EVB"
48 #define CONFIG_EXTRA_ENV_SETTINGS \
51 "u-boot=u-boot.bin\0" \
52 "load=tftp ${loadaddr) ${u-boot}\0" \
53 "upd=run load; run prog\0" \
54 "prog=prot off ffe00000 ffe3ffff;" \
55 "era ffe00000 ffe3ffff;" \
56 "cp.b ${loadaddr} ffe00000 ${filesize};"\
60 #define CONFIG_PRAM 512 /* 512 KB */
62 #define CONFIG_SYS_CLK 75000000
63 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
65 #define CONFIG_SYS_MBAR 0x40000000
68 * Low Level Configuration Settings
69 * (address mappings, register initial values, etc.)
70 * You should know what you are doing if you make changes here.
72 /*-----------------------------------------------------------------------
73 * Definitions for initial stack pointer and data area (in DPRAM)
75 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
76 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
77 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
78 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
79 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
81 /*-----------------------------------------------------------------------
82 * Start addresses for the final memory configuration
83 * (Set up by the startup code)
84 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
86 #define CONFIG_SYS_SDRAM_BASE 0x00000000
87 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
89 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
90 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
92 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
95 * For booting Linux, the board info and command line data
96 * have to be in the first 8 MB of memory, since this is
97 * the maximum mapped by the Linux kernel during initialization ??
99 /* Initial Memory map for Linux */
100 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
101 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
103 /*-----------------------------------------------------------------------
106 #ifdef CONFIG_SYS_FLASH_CFI
107 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
108 #ifdef CONFIG_NORFLASH_PS32BIT
109 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
111 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
113 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
116 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
118 /* Configuration for environment
119 * Environment is embedded in u-boot in the second sector of the flash
122 #define LDS_BOARD_TEXT \
123 . = DEFINED(env_offset) ? env_offset : .; \
124 env/embedded.o(.text);
126 /*-----------------------------------------------------------------------
127 * Cache Configuration
130 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
131 CONFIG_SYS_INIT_RAM_SIZE - 8)
132 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
133 CONFIG_SYS_INIT_RAM_SIZE - 4)
134 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
135 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
136 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
137 CF_ACR_EN | CF_ACR_SM_ALL)
138 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
139 CF_CACR_CEIB | CF_CACR_DCM | \
142 /*-----------------------------------------------------------------------
143 * Chipselect bank definitions
146 * CS0 - NOR Flash 1, 2, 4, or 8MB
155 #ifdef CONFIG_NORFLASH_PS32BIT
156 # define CONFIG_SYS_CS0_BASE 0xFFC00000
157 # define CONFIG_SYS_CS0_MASK 0x003f0001
158 # define CONFIG_SYS_CS0_CTRL 0x00001D00
160 # define CONFIG_SYS_CS0_BASE 0xFFE00000
161 # define CONFIG_SYS_CS0_MASK 0x001f0001
162 # define CONFIG_SYS_CS0_CTRL 0x00001D80
165 #endif /* _M5329EVB_H */