1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
26 # define CONFIG_SYS_DISCOVER_PHY
27 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
28 # ifndef CONFIG_SYS_DISCOVER_PHY
29 # define FECDUPLEX FULL
30 # define FECSPEED _100BASET
31 # endif /* CONFIG_SYS_DISCOVER_PHY */
38 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
39 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
40 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
42 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
44 # define CONFIG_IPADDR 192.162.1.2
45 # define CONFIG_NETMASK 255.255.255.0
46 # define CONFIG_SERVERIP 192.162.1.1
47 # define CONFIG_GATEWAYIP 192.162.1.1
50 #define CONFIG_HOSTNAME "M5235EVB"
51 #define CONFIG_EXTRA_ENV_SETTINGS \
54 "u-boot=u-boot.bin\0" \
55 "load=tftp ${loadaddr) ${u-boot}\0" \
56 "upd=run load; run prog\0" \
57 "prog=prot off ffe00000 ffe3ffff;" \
58 "era ffe00000 ffe3ffff;" \
59 "cp.b ${loadaddr} ffe00000 ${filesize};"\
63 #define CONFIG_PRAM 512 /* 512 KB */
65 #define CONFIG_SYS_CLK 75000000
66 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
68 #define CONFIG_SYS_MBAR 0x40000000
71 * Low Level Configuration Settings
72 * (address mappings, register initial values, etc.)
73 * You should know what you are doing if you make changes here.
75 /*-----------------------------------------------------------------------
76 * Definitions for initial stack pointer and data area (in DPRAM)
78 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
79 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
80 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
81 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
82 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
84 /*-----------------------------------------------------------------------
85 * Start addresses for the final memory configuration
86 * (Set up by the startup code)
87 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
89 #define CONFIG_SYS_SDRAM_BASE 0x00000000
90 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
92 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
93 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
95 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
98 * For booting Linux, the board info and command line data
99 * have to be in the first 8 MB of memory, since this is
100 * the maximum mapped by the Linux kernel during initialization ??
102 /* Initial Memory map for Linux */
103 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
104 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
106 /*-----------------------------------------------------------------------
109 #ifdef CONFIG_SYS_FLASH_CFI
110 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
111 #ifdef NORFLASH_PS32BIT
112 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
114 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
116 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
119 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
121 /* Configuration for environment
122 * Environment is embedded in u-boot in the second sector of the flash
125 #define LDS_BOARD_TEXT \
126 . = DEFINED(env_offset) ? env_offset : .; \
127 env/embedded.o(.text);
129 /*-----------------------------------------------------------------------
130 * Cache Configuration
133 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
134 CONFIG_SYS_INIT_RAM_SIZE - 8)
135 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
136 CONFIG_SYS_INIT_RAM_SIZE - 4)
137 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
138 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
139 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
140 CF_ACR_EN | CF_ACR_SM_ALL)
141 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
142 CF_CACR_CEIB | CF_CACR_DCM | \
145 /*-----------------------------------------------------------------------
146 * Chipselect bank definitions
149 * CS0 - NOR Flash 1, 2, 4, or 8MB
158 #ifdef NORFLASH_PS32BIT
159 # define CONFIG_SYS_CS0_BASE 0xFFC00000
160 # define CONFIG_SYS_CS0_MASK 0x003f0001
161 # define CONFIG_SYS_CS0_CTRL 0x00001D00
163 # define CONFIG_SYS_CS0_BASE 0xFFE00000
164 # define CONFIG_SYS_CS0_MASK 0x001f0001
165 # define CONFIG_SYS_CS0_CTRL 0x00001D80
168 #endif /* _M5329EVB_H */