1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
26 # define CONFIG_MII_INIT 1
27 # define CONFIG_SYS_DISCOVER_PHY
28 # define CONFIG_SYS_RX_ETH_BUFFER 8
29 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
30 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
31 # ifndef CONFIG_SYS_DISCOVER_PHY
32 # define FECDUPLEX FULL
33 # define FECSPEED _100BASET
35 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
36 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
38 # endif /* CONFIG_SYS_DISCOVER_PHY */
45 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
46 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
47 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
49 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
51 # define CONFIG_IPADDR 192.162.1.2
52 # define CONFIG_NETMASK 255.255.255.0
53 # define CONFIG_SERVERIP 192.162.1.1
54 # define CONFIG_GATEWAYIP 192.162.1.1
57 #define CONFIG_HOSTNAME "M5235EVB"
58 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "u-boot=u-boot.bin\0" \
62 "load=tftp ${loadaddr) ${u-boot}\0" \
63 "upd=run load; run prog\0" \
64 "prog=prot off ffe00000 ffe3ffff;" \
65 "era ffe00000 ffe3ffff;" \
66 "cp.b ${loadaddr} ffe00000 ${filesize};"\
70 #define CONFIG_PRAM 512 /* 512 KB */
72 #define CONFIG_SYS_CLK 75000000
73 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
75 #define CONFIG_SYS_MBAR 0x40000000
78 * Low Level Configuration Settings
79 * (address mappings, register initial values, etc.)
80 * You should know what you are doing if you make changes here.
82 /*-----------------------------------------------------------------------
83 * Definitions for initial stack pointer and data area (in DPRAM)
85 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
86 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
87 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
88 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
89 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
91 /*-----------------------------------------------------------------------
92 * Start addresses for the final memory configuration
93 * (Set up by the startup code)
94 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
96 #define CONFIG_SYS_SDRAM_BASE 0x00000000
97 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
99 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
100 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
102 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
105 * For booting Linux, the board info and command line data
106 * have to be in the first 8 MB of memory, since this is
107 * the maximum mapped by the Linux kernel during initialization ??
109 /* Initial Memory map for Linux */
110 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
111 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
113 /*-----------------------------------------------------------------------
116 #ifdef CONFIG_SYS_FLASH_CFI
117 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
118 #ifdef NORFLASH_PS32BIT
119 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
121 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
123 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
126 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
128 /* Configuration for environment
129 * Environment is embedded in u-boot in the second sector of the flash
132 #define LDS_BOARD_TEXT \
133 . = DEFINED(env_offset) ? env_offset : .; \
134 env/embedded.o(.text);
136 /*-----------------------------------------------------------------------
137 * Cache Configuration
140 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
141 CONFIG_SYS_INIT_RAM_SIZE - 8)
142 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
143 CONFIG_SYS_INIT_RAM_SIZE - 4)
144 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
145 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
146 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
147 CF_ACR_EN | CF_ACR_SM_ALL)
148 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
149 CF_CACR_CEIB | CF_CACR_DCM | \
152 /*-----------------------------------------------------------------------
153 * Chipselect bank definitions
156 * CS0 - NOR Flash 1, 2, 4, or 8MB
165 #ifdef NORFLASH_PS32BIT
166 # define CONFIG_SYS_CS0_BASE 0xFFC00000
167 # define CONFIG_SYS_CS0_MASK 0x003f0001
168 # define CONFIG_SYS_CS0_CTRL 0x00001D00
170 # define CONFIG_SYS_CS0_BASE 0xFFE00000
171 # define CONFIG_SYS_CS0_MASK 0x001f0001
172 # define CONFIG_SYS_CS0_CTRL 0x00001D80
175 #endif /* _M5329EVB_H */