1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
26 # define CONFIG_MII_INIT 1
27 # define CONFIG_SYS_DISCOVER_PHY
28 # define CONFIG_SYS_RX_ETH_BUFFER 8
29 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
30 # ifndef CONFIG_SYS_DISCOVER_PHY
31 # define FECDUPLEX FULL
32 # define FECSPEED _100BASET
33 # endif /* CONFIG_SYS_DISCOVER_PHY */
40 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
41 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
42 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
44 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
46 # define CONFIG_IPADDR 192.162.1.2
47 # define CONFIG_NETMASK 255.255.255.0
48 # define CONFIG_SERVERIP 192.162.1.1
49 # define CONFIG_GATEWAYIP 192.162.1.1
52 #define CONFIG_HOSTNAME "M5235EVB"
53 #define CONFIG_EXTRA_ENV_SETTINGS \
56 "u-boot=u-boot.bin\0" \
57 "load=tftp ${loadaddr) ${u-boot}\0" \
58 "upd=run load; run prog\0" \
59 "prog=prot off ffe00000 ffe3ffff;" \
60 "era ffe00000 ffe3ffff;" \
61 "cp.b ${loadaddr} ffe00000 ${filesize};"\
65 #define CONFIG_PRAM 512 /* 512 KB */
67 #define CONFIG_SYS_CLK 75000000
68 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
70 #define CONFIG_SYS_MBAR 0x40000000
73 * Low Level Configuration Settings
74 * (address mappings, register initial values, etc.)
75 * You should know what you are doing if you make changes here.
77 /*-----------------------------------------------------------------------
78 * Definitions for initial stack pointer and data area (in DPRAM)
80 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
81 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
82 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
83 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
84 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86 /*-----------------------------------------------------------------------
87 * Start addresses for the final memory configuration
88 * (Set up by the startup code)
89 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
91 #define CONFIG_SYS_SDRAM_BASE 0x00000000
92 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
94 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
95 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
97 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
100 * For booting Linux, the board info and command line data
101 * have to be in the first 8 MB of memory, since this is
102 * the maximum mapped by the Linux kernel during initialization ??
104 /* Initial Memory map for Linux */
105 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
106 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
108 /*-----------------------------------------------------------------------
111 #ifdef CONFIG_SYS_FLASH_CFI
112 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
113 #ifdef NORFLASH_PS32BIT
114 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
116 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
118 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
121 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
123 /* Configuration for environment
124 * Environment is embedded in u-boot in the second sector of the flash
127 #define LDS_BOARD_TEXT \
128 . = DEFINED(env_offset) ? env_offset : .; \
129 env/embedded.o(.text);
131 /*-----------------------------------------------------------------------
132 * Cache Configuration
135 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
136 CONFIG_SYS_INIT_RAM_SIZE - 8)
137 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
138 CONFIG_SYS_INIT_RAM_SIZE - 4)
139 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
140 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
141 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
142 CF_ACR_EN | CF_ACR_SM_ALL)
143 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
144 CF_CACR_CEIB | CF_CACR_DCM | \
147 /*-----------------------------------------------------------------------
148 * Chipselect bank definitions
151 * CS0 - NOR Flash 1, 2, 4, or 8MB
160 #ifdef NORFLASH_PS32BIT
161 # define CONFIG_SYS_CS0_BASE 0xFFC00000
162 # define CONFIG_SYS_CS0_MASK 0x003f0001
163 # define CONFIG_SYS_CS0_CTRL 0x00001D00
165 # define CONFIG_SYS_CS0_BASE 0xFFE00000
166 # define CONFIG_SYS_CS0_MASK 0x001f0001
167 # define CONFIG_SYS_CS0_CTRL 0x00001D80
170 #endif /* _M5329EVB_H */