1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CFG_SYS_UART_PORT (0)
24 #define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
25 #define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
26 #define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
28 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
30 # define CONFIG_IPADDR 192.162.1.2
31 # define CONFIG_NETMASK 255.255.255.0
32 # define CONFIG_SERVERIP 192.162.1.1
33 # define CONFIG_GATEWAYIP 192.162.1.1
36 #define CONFIG_HOSTNAME "M5235EVB"
37 #define CONFIG_EXTRA_ENV_SETTINGS \
40 "u-boot=u-boot.bin\0" \
41 "load=tftp ${loadaddr) ${u-boot}\0" \
42 "upd=run load; run prog\0" \
43 "prog=prot off ffe00000 ffe3ffff;" \
44 "era ffe00000 ffe3ffff;" \
45 "cp.b ${loadaddr} ffe00000 ${filesize};"\
49 #define CONFIG_PRAM 512 /* 512 KB */
51 #define CFG_SYS_CLK 75000000
52 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2
54 #define CFG_SYS_MBAR 0x40000000
57 * Low Level Configuration Settings
58 * (address mappings, register initial values, etc.)
59 * You should know what you are doing if you make changes here.
61 /*-----------------------------------------------------------------------
62 * Definitions for initial stack pointer and data area (in DPRAM)
64 #define CFG_SYS_INIT_RAM_ADDR 0x20000000
65 #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
66 #define CFG_SYS_INIT_RAM_CTRL 0x21
68 /*-----------------------------------------------------------------------
69 * Start addresses for the final memory configuration
70 * (Set up by the startup code)
71 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
73 #define CFG_SYS_SDRAM_BASE 0x00000000
74 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
77 * For booting Linux, the board info and command line data
78 * have to be in the first 8 MB of memory, since this is
79 * the maximum mapped by the Linux kernel during initialization ??
81 /* Initial Memory map for Linux */
82 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
84 /*-----------------------------------------------------------------------
87 #ifdef CONFIG_SYS_FLASH_CFI
88 # define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
91 #define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
93 /* Configuration for environment
94 * Environment is embedded in u-boot in the second sector of the flash
97 #define LDS_BOARD_TEXT \
98 . = DEFINED(env_offset) ? env_offset : .; \
99 env/embedded.o(.text);
101 /*-----------------------------------------------------------------------
102 * Cache Configuration
105 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
106 CFG_SYS_INIT_RAM_SIZE - 8)
107 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
108 CFG_SYS_INIT_RAM_SIZE - 4)
109 #define CFG_SYS_ICACHE_INV (CF_CACR_CINV)
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
111 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
112 CF_ACR_EN | CF_ACR_SM_ALL)
113 #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
114 CF_CACR_CEIB | CF_CACR_DCM | \
117 /*-----------------------------------------------------------------------
118 * Chipselect bank definitions
121 * CS0 - NOR Flash 1, 2, 4, or 8MB
130 #ifdef CONFIG_NORFLASH_PS32BIT
131 # define CFG_SYS_CS0_BASE 0xFFC00000
132 # define CFG_SYS_CS0_MASK 0x003f0001
133 # define CFG_SYS_CS0_CTRL 0x00001D00
135 # define CFG_SYS_CS0_BASE 0xFFE00000
136 # define CFG_SYS_CS0_MASK 0x001f0001
137 # define CFG_SYS_CS0_CTRL 0x00001D80
140 #endif /* _M5329EVB_H */