1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT (0)
24 #undef CONFIG_WATCHDOG
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
30 #define CONFIG_BOOTP_BOOTFILESIZE
34 # define CONFIG_MII_INIT 1
35 # define CONFIG_SYS_DISCOVER_PHY
36 # define CONFIG_SYS_RX_ETH_BUFFER 8
37 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
39 # define CONFIG_SYS_FEC0_PINMUX 0
40 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
41 # define MCFFEC_TOUT_LOOP 50000
42 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
43 # ifndef CONFIG_SYS_DISCOVER_PHY
44 # define FECDUPLEX FULL
45 # define FECSPEED _100BASET
47 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
50 # endif /* CONFIG_SYS_DISCOVER_PHY */
58 #define CONFIG_SYS_I2C
59 #define CONFIG_SYS_i2C_FSL
60 #define CONFIG_SYS_FSL_I2C_SPEED 80000
61 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
62 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
63 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
64 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
65 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
66 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
68 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
69 #define CONFIG_BOOTFILE "u-boot.bin"
71 # define CONFIG_IPADDR 192.162.1.2
72 # define CONFIG_NETMASK 255.255.255.0
73 # define CONFIG_SERVERIP 192.162.1.1
74 # define CONFIG_GATEWAYIP 192.162.1.1
77 #define CONFIG_HOSTNAME "M5235EVB"
78 #define CONFIG_EXTRA_ENV_SETTINGS \
81 "u-boot=u-boot.bin\0" \
82 "load=tftp ${loadaddr) ${u-boot}\0" \
83 "upd=run load; run prog\0" \
84 "prog=prot off ffe00000 ffe3ffff;" \
85 "era ffe00000 ffe3ffff;" \
86 "cp.b ${loadaddr} ffe00000 ${filesize};"\
90 #define CONFIG_PRAM 512 /* 512 KB */
92 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
94 #define CONFIG_SYS_CLK 75000000
95 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
97 #define CONFIG_SYS_MBAR 0x40000000
100 * Low Level Configuration Settings
101 * (address mappings, register initial values, etc.)
102 * You should know what you are doing if you make changes here.
104 /*-----------------------------------------------------------------------
105 * Definitions for initial stack pointer and data area (in DPRAM)
107 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
108 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
109 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
110 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
111 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
113 /*-----------------------------------------------------------------------
114 * Start addresses for the final memory configuration
115 * (Set up by the startup code)
116 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
118 #define CONFIG_SYS_SDRAM_BASE 0x00000000
119 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
121 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
122 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
124 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
125 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
127 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
128 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
131 * For booting Linux, the board info and command line data
132 * have to be in the first 8 MB of memory, since this is
133 * the maximum mapped by the Linux kernel during initialization ??
135 /* Initial Memory map for Linux */
136 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
137 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
139 /*-----------------------------------------------------------------------
142 #ifdef CONFIG_SYS_FLASH_CFI
143 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
144 #ifdef NORFLASH_PS32BIT
145 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
147 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
149 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
150 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
153 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
155 /* Configuration for environment
156 * Environment is embedded in u-boot in the second sector of the flash
159 #define LDS_BOARD_TEXT \
160 . = DEFINED(env_offset) ? env_offset : .; \
161 env/embedded.o(.text);
163 #ifdef NORFLASH_PS32BIT
164 # define CONFIG_ENV_OFFSET (0x8000)
165 # define CONFIG_ENV_SIZE 0x4000
166 # define CONFIG_ENV_SECT_SIZE 0x4000
168 # define CONFIG_ENV_OFFSET (0x4000)
169 # define CONFIG_ENV_SIZE 0x2000
170 # define CONFIG_ENV_SECT_SIZE 0x2000
173 /*-----------------------------------------------------------------------
174 * Cache Configuration
176 #define CONFIG_SYS_CACHELINE_SIZE 16
178 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
179 CONFIG_SYS_INIT_RAM_SIZE - 8)
180 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
181 CONFIG_SYS_INIT_RAM_SIZE - 4)
182 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
183 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
184 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
185 CF_ACR_EN | CF_ACR_SM_ALL)
186 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
187 CF_CACR_CEIB | CF_CACR_DCM | \
190 /*-----------------------------------------------------------------------
191 * Chipselect bank definitions
194 * CS0 - NOR Flash 1, 2, 4, or 8MB
203 #ifdef NORFLASH_PS32BIT
204 # define CONFIG_SYS_CS0_BASE 0xFFC00000
205 # define CONFIG_SYS_CS0_MASK 0x003f0001
206 # define CONFIG_SYS_CS0_CTRL 0x00001D00
208 # define CONFIG_SYS_CS0_BASE 0xFFE00000
209 # define CONFIG_SYS_CS0_MASK 0x001f0001
210 # define CONFIG_SYS_CS0_CTRL 0x00001D80
213 #endif /* _M5329EVB_H */