1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
28 #define CONFIG_BOOTP_BOOTFILESIZE
31 # define CONFIG_MII_INIT 1
32 # define CONFIG_SYS_DISCOVER_PHY
33 # define CONFIG_SYS_RX_ETH_BUFFER 8
34 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
35 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
36 # ifndef CONFIG_SYS_DISCOVER_PHY
37 # define FECDUPLEX FULL
38 # define FECSPEED _100BASET
40 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 # endif /* CONFIG_SYS_DISCOVER_PHY */
50 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
51 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
52 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
54 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
56 # define CONFIG_IPADDR 192.162.1.2
57 # define CONFIG_NETMASK 255.255.255.0
58 # define CONFIG_SERVERIP 192.162.1.1
59 # define CONFIG_GATEWAYIP 192.162.1.1
62 #define CONFIG_HOSTNAME "M5235EVB"
63 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "u-boot=u-boot.bin\0" \
67 "load=tftp ${loadaddr) ${u-boot}\0" \
68 "upd=run load; run prog\0" \
69 "prog=prot off ffe00000 ffe3ffff;" \
70 "era ffe00000 ffe3ffff;" \
71 "cp.b ${loadaddr} ffe00000 ${filesize};"\
75 #define CONFIG_PRAM 512 /* 512 KB */
77 #define CONFIG_SYS_CLK 75000000
78 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
80 #define CONFIG_SYS_MBAR 0x40000000
83 * Low Level Configuration Settings
84 * (address mappings, register initial values, etc.)
85 * You should know what you are doing if you make changes here.
87 /*-----------------------------------------------------------------------
88 * Definitions for initial stack pointer and data area (in DPRAM)
90 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
91 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
92 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
93 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
94 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
96 /*-----------------------------------------------------------------------
97 * Start addresses for the final memory configuration
98 * (Set up by the startup code)
99 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
101 #define CONFIG_SYS_SDRAM_BASE 0x00000000
102 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
104 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
105 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
107 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
110 * For booting Linux, the board info and command line data
111 * have to be in the first 8 MB of memory, since this is
112 * the maximum mapped by the Linux kernel during initialization ??
114 /* Initial Memory map for Linux */
115 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
116 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
118 /*-----------------------------------------------------------------------
121 #ifdef CONFIG_SYS_FLASH_CFI
122 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
123 #ifdef NORFLASH_PS32BIT
124 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
126 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
128 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
131 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
133 /* Configuration for environment
134 * Environment is embedded in u-boot in the second sector of the flash
137 #define LDS_BOARD_TEXT \
138 . = DEFINED(env_offset) ? env_offset : .; \
139 env/embedded.o(.text);
141 /*-----------------------------------------------------------------------
142 * Cache Configuration
145 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
146 CONFIG_SYS_INIT_RAM_SIZE - 8)
147 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
148 CONFIG_SYS_INIT_RAM_SIZE - 4)
149 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
150 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
151 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
152 CF_ACR_EN | CF_ACR_SM_ALL)
153 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
154 CF_CACR_CEIB | CF_CACR_DCM | \
157 /*-----------------------------------------------------------------------
158 * Chipselect bank definitions
161 * CS0 - NOR Flash 1, 2, 4, or 8MB
170 #ifdef NORFLASH_PS32BIT
171 # define CONFIG_SYS_CS0_BASE 0xFFC00000
172 # define CONFIG_SYS_CS0_MASK 0x003f0001
173 # define CONFIG_SYS_CS0_CTRL 0x00001D00
175 # define CONFIG_SYS_CS0_BASE 0xFFE00000
176 # define CONFIG_SYS_CS0_MASK 0x001f0001
177 # define CONFIG_SYS_CS0_CTRL 0x00001D80
180 #endif /* _M5329EVB_H */