include/configs/M52277EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF52277 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M52277EVB_H
  15 #define _M52277EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M52277EVB        /* M52277EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #undef CONFIG_WATCHDOG
  27
  28 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 /* Command line configuration */
  39 #define CONFIG_CMD_DATE
  40 #define CONFIG_CMD_JFFS2
  41 #define CONFIG_CMD_REGINFO
  42 #undef CONFIG_CMD_BMP
  43
  44 #define CONFIG_HOSTNAME                 M52277EVB
  45 #define CONFIG_SYS_UBOOT_END            0x3FFFF
  46 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  47 #ifdef CONFIG_SYS_STMICRO_BOOT
  48 /* ST Micro serial flash */
  49 #define CONFIG_EXTRA_ENV_SETTINGS               \
  50         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  51         "loadaddr=0x40010000\0"                 \
  52         "uboot=u-boot.bin\0"                    \
  53         "load=loadb ${loadaddr} ${baudrate};"   \
  54         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  55         "upd=run load; run prog\0"              \
  56         "prog=sf probe 0:2 10000 1;"            \
  57         "sf erase 0 30000;"                     \
  58         "sf write ${loadaddr} 0 30000;"         \
  59         "save\0"                                \
  60         ""
  61 #endif
  62 #ifdef CONFIG_SYS_SPANSION_BOOT
  63 #define CONFIG_EXTRA_ENV_SETTINGS               \
  64         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  65         "loadaddr=0x40010000\0"                 \
  66         "uboot=u-boot.bin\0"                    \
  67         "load=loadb ${loadaddr} ${baudrate}\0"  \
  68         "upd=run load; run prog\0"              \
  69         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
  70         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
  71         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
  72         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
  73         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
  74         " ${filesize}; save\0"                  \
  75         "updsbf=run loadsbf; run progsbf\0"     \
  76         "loadsbf=loadb ${loadaddr} ${baudrate};"        \
  77         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  78         "progsbf=sf probe 0:2 10000 1;"         \
  79         "sf erase 0 30000;"                     \
  80         "sf write ${loadaddr} 0 30000;"         \
  81         ""
  82 #endif
  83
  84 /* LCD */
  85 #ifdef CONFIG_CMD_BMP
  86 #define CONFIG_SPLASH_SCREEN
  87 #define CONFIG_LCD_LOGO
  88 #define CONFIG_SHARP_LQ035Q7DH06
  89 #endif
  90
  91 /* USB */
  92 #ifdef CONFIG_CMD_USB
  93 #define CONFIG_USB_EHCI
  94 #define CONFIG_SYS_USB_EHCI_REGS_BASE   0xFC0B0000
  95 #define CONFIG_SYS_USB_EHCI_CPU_INIT
  96 #endif
  97
  98 /* Realtime clock */
  99 #define CONFIG_MCFRTC
 100 #undef RTC_DEBUG
 101 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 102
 103 /* Timer */
 104 #define CONFIG_MCFTMR
 105 #undef CONFIG_MCFPIT
 106
 107 /* I2c */
 108 #define CONFIG_SYS_I2C
 109 #define CONFIG_SYS_I2C_FSL
 110 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 111 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 112 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 113 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 114
 115 /* DSPI and Serial Flash */
 116 #define CONFIG_CF_SPI
 117 #define CONFIG_CF_DSPI
 118 #define CONFIG_HARD_SPI
 119 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 120 #ifdef CONFIG_CMD_SPI
 121 #       define CONFIG_SYS_DSPI_CS2
 122
 123 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 124                                          DSPI_CTAR_PCSSCK_1CLK | \
 125                                          DSPI_CTAR_PASC(0) | \
 126                                          DSPI_CTAR_PDT(0) | \
 127                                          DSPI_CTAR_CSSCK(0) | \
 128                                          DSPI_CTAR_ASC(0) | \
 129                                          DSPI_CTAR_DT(1))
 130 #endif
 131
 132 /* Input, PCI, Flexbus, and VCO */
 133 #define CONFIG_EXTRA_CLOCK
 134
 135 #define CONFIG_SYS_INPUT_CLKSRC 16000000
 136
 137 #define CONFIG_PRAM             2048    /* 2048 KB */
 138
 139 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 140
 141 #if defined(CONFIG_CMD_KGDB)
 142 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 143 #else
 144 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 145 #endif
 146 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 147 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 148 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 149
 150 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x10000)
 151
 152 #define CONFIG_SYS_MBAR         0xFC000000
 153
 154 /*
 155  * Low Level Configuration Settings
 156  * (address mappings, register initial values, etc.)
 157  * You should know what you are doing if you make changes here.
 158  */
 159
 160 /*
 161  * Definitions for initial stack pointer and data area (in DPRAM)
 162  */
 163 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 164 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 165 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 166 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 167 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 168 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 169
 170 /*
 171  * Start addresses for the final memory configuration
 172  * (Set up by the startup code)
 173  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 174  */
 175 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 176 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 177 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 178 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 179 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 180 #define CONFIG_SYS_SDRAM_EMOD           0x81810000
 181 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 182 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x00
 183
 184 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 185 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 186
 187 #ifdef CONFIG_CF_SBF
 188 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 189 #else
 190 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 191 #endif
 192 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 193 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 194 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 195
 196 /* Initial Memory map for Linux */
 197 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 198 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 199
 200 /*
 201  * Configuration for environment
 202  * Environment is not embedded in u-boot. First time runing may have env
 203  * crc error warning if there is no correct environment on the flash.
 204  */
 205 #ifdef CONFIG_CF_SBF
 206 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 207 #       define CONFIG_ENV_SPI_CS        2
 208 #else
 209 #       define CONFIG_ENV_IS_IN_FLASH   1
 210 #endif
 211 #define CONFIG_ENV_OVERWRITE            1
 212
 213 /*-----------------------------------------------------------------------
 214  * FLASH organization
 215  */
 216 #ifdef CONFIG_SYS_STMICRO_BOOT
 217 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 218 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 219 #       define CONFIG_ENV_OFFSET        0x30000
 220 #       define CONFIG_ENV_SIZE          0x1000
 221 #       define CONFIG_ENV_SECT_SIZE     0x10000
 222 #endif
 223 #ifdef CONFIG_SYS_SPANSION_BOOT
 224 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 225 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 226 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 227 #       define CONFIG_ENV_SIZE          0x1000
 228 #       define CONFIG_ENV_SECT_SIZE     0x8000
 229 #endif
 230
 231 #define CONFIG_SYS_FLASH_CFI
 232 #ifdef CONFIG_SYS_FLASH_CFI
 233 #       define CONFIG_FLASH_CFI_DRIVER  1
 234 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 235 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 236 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 237 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 238 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 239 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 240 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 241 #       define CONFIG_SYS_FLASH_CHECKSUM
 242 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 243 #endif
 244
 245 #define LDS_BOARD_TEXT \
 246         arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
 247         arch/m68k/lib/built-in.o            (.text*)
 248
 249 /*
 250  * This is setting for JFFS2 support in u-boot.
 251  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 252  */
 253 #ifdef CONFIG_CMD_JFFS2
 254 #       define CONFIG_JFFS2_DEV         "nor0"
 255 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x40000)
 256 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
 257 #endif
 258
 259 /*-----------------------------------------------------------------------
 260  * Cache Configuration
 261  */
 262 #define CONFIG_SYS_CACHELINE_SIZE       16
 263
 264 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 265                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 266 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 267                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 268 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 269 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 270                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 271                                          CF_ACR_EN | CF_ACR_SM_ALL)
 272 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 273                                          CF_CACR_DISD | CF_CACR_INVI | \
 274                                          CF_CACR_CEIB | CF_CACR_DCM | \
 275                                          CF_CACR_EUSP)
 276
 277 /*-----------------------------------------------------------------------
 278  * Memory bank definitions
 279  */
 280 /*
 281  * CS0 - NOR Flash
 282  * CS1 - Available
 283  * CS2 - Available
 284  * CS3 - Available
 285  * CS4 - Available
 286  * CS5 - Available
 287  */
 288
 289 #ifdef CONFIG_CF_SBF
 290 #define CONFIG_SYS_CS0_BASE             0x04000000
 291 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 292 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 293 #else
 294 #define CONFIG_SYS_CS0_BASE             0x00000000
 295 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 296 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 297 #endif
 298
 299 #endif                          /* _M52277EVB_H */