include/configs/M52277EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF52277 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M52277EVB_H
  15 #define _M52277EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M52277EVB        /* M52277EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #undef CONFIG_WATCHDOG
  27
  28 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 /* Command line configuration */
  39 #define CONFIG_CMD_DATE
  40 #define CONFIG_CMD_JFFS2
  41 #define CONFIG_CMD_REGINFO
  42
  43 #define CONFIG_HOSTNAME                 M52277EVB
  44 #define CONFIG_SYS_UBOOT_END            0x3FFFF
  45 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  46 #ifdef CONFIG_SYS_STMICRO_BOOT
  47 /* ST Micro serial flash */
  48 #define CONFIG_EXTRA_ENV_SETTINGS               \
  49         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  50         "loadaddr=0x40010000\0"                 \
  51         "uboot=u-boot.bin\0"                    \
  52         "load=loadb ${loadaddr} ${baudrate};"   \
  53         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  54         "upd=run load; run prog\0"              \
  55         "prog=sf probe 0:2 10000 1;"            \
  56         "sf erase 0 30000;"                     \
  57         "sf write ${loadaddr} 0 30000;"         \
  58         "save\0"                                \
  59         ""
  60 #endif
  61 #ifdef CONFIG_SYS_SPANSION_BOOT
  62 #define CONFIG_EXTRA_ENV_SETTINGS               \
  63         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  64         "loadaddr=0x40010000\0"                 \
  65         "uboot=u-boot.bin\0"                    \
  66         "load=loadb ${loadaddr} ${baudrate}\0"  \
  67         "upd=run load; run prog\0"              \
  68         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
  69         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
  70         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
  71         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
  72         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
  73         " ${filesize}; save\0"                  \
  74         "updsbf=run loadsbf; run progsbf\0"     \
  75         "loadsbf=loadb ${loadaddr} ${baudrate};"        \
  76         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  77         "progsbf=sf probe 0:2 10000 1;"         \
  78         "sf erase 0 30000;"                     \
  79         "sf write ${loadaddr} 0 30000;"         \
  80         ""
  81 #endif
  82
  83 /* LCD */
  84 #ifdef CONFIG_CMD_BMP
  85 #define CONFIG_SPLASH_SCREEN
  86 #define CONFIG_LCD_LOGO
  87 #define CONFIG_SHARP_LQ035Q7DH06
  88 #endif
  89
  90 /* USB */
  91 #ifdef CONFIG_CMD_USB
  92 #define CONFIG_USB_EHCI
  93 #define CONFIG_SYS_USB_EHCI_REGS_BASE   0xFC0B0000
  94 #define CONFIG_SYS_USB_EHCI_CPU_INIT
  95 #endif
  96
  97 /* Realtime clock */
  98 #define CONFIG_MCFRTC
  99 #undef RTC_DEBUG
 100 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 101
 102 /* Timer */
 103 #define CONFIG_MCFTMR
 104 #undef CONFIG_MCFPIT
 105
 106 /* I2c */
 107 #define CONFIG_SYS_I2C
 108 #define CONFIG_SYS_I2C_FSL
 109 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 110 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 111 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 112 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 113
 114 /* DSPI and Serial Flash */
 115 #define CONFIG_CF_SPI
 116 #define CONFIG_CF_DSPI
 117 #define CONFIG_HARD_SPI
 118 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 119 #ifdef CONFIG_CMD_SPI
 120 #       define CONFIG_SYS_DSPI_CS2
 121
 122 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 123                                          DSPI_CTAR_PCSSCK_1CLK | \
 124                                          DSPI_CTAR_PASC(0) | \
 125                                          DSPI_CTAR_PDT(0) | \
 126                                          DSPI_CTAR_CSSCK(0) | \
 127                                          DSPI_CTAR_ASC(0) | \
 128                                          DSPI_CTAR_DT(1))
 129 #endif
 130
 131 /* Input, PCI, Flexbus, and VCO */
 132 #define CONFIG_EXTRA_CLOCK
 133
 134 #define CONFIG_SYS_INPUT_CLKSRC 16000000
 135
 136 #define CONFIG_PRAM             2048    /* 2048 KB */
 137
 138 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 139
 140 #if defined(CONFIG_CMD_KGDB)
 141 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 142 #else
 143 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 144 #endif
 145 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 146 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 147 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 148
 149 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x10000)
 150
 151 #define CONFIG_SYS_MBAR         0xFC000000
 152
 153 /*
 154  * Low Level Configuration Settings
 155  * (address mappings, register initial values, etc.)
 156  * You should know what you are doing if you make changes here.
 157  */
 158
 159 /*
 160  * Definitions for initial stack pointer and data area (in DPRAM)
 161  */
 162 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 163 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 164 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 166 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 167 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 168
 169 /*
 170  * Start addresses for the final memory configuration
 171  * (Set up by the startup code)
 172  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 173  */
 174 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 175 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 176 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 177 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 178 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 179 #define CONFIG_SYS_SDRAM_EMOD           0x81810000
 180 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 181 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x00
 182
 183 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 184 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 185
 186 #ifdef CONFIG_CF_SBF
 187 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 188 #else
 189 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 190 #endif
 191 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 192 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 193 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 194
 195 /* Initial Memory map for Linux */
 196 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 197 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 198
 199 /*
 200  * Configuration for environment
 201  * Environment is not embedded in u-boot. First time runing may have env
 202  * crc error warning if there is no correct environment on the flash.
 203  */
 204 #ifdef CONFIG_CF_SBF
 205 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 206 #       define CONFIG_ENV_SPI_CS        2
 207 #else
 208 #       define CONFIG_ENV_IS_IN_FLASH   1
 209 #endif
 210 #define CONFIG_ENV_OVERWRITE            1
 211
 212 /*-----------------------------------------------------------------------
 213  * FLASH organization
 214  */
 215 #ifdef CONFIG_SYS_STMICRO_BOOT
 216 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 217 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 218 #       define CONFIG_ENV_OFFSET        0x30000
 219 #       define CONFIG_ENV_SIZE          0x1000
 220 #       define CONFIG_ENV_SECT_SIZE     0x10000
 221 #endif
 222 #ifdef CONFIG_SYS_SPANSION_BOOT
 223 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 224 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 225 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 226 #       define CONFIG_ENV_SIZE          0x1000
 227 #       define CONFIG_ENV_SECT_SIZE     0x8000
 228 #endif
 229
 230 #define CONFIG_SYS_FLASH_CFI
 231 #ifdef CONFIG_SYS_FLASH_CFI
 232 #       define CONFIG_FLASH_CFI_DRIVER  1
 233 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 234 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 235 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 236 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 237 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 238 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 239 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 240 #       define CONFIG_SYS_FLASH_CHECKSUM
 241 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 242 #endif
 243
 244 #define LDS_BOARD_TEXT \
 245         arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
 246         arch/m68k/lib/built-in.o            (.text*)
 247
 248 /*
 249  * This is setting for JFFS2 support in u-boot.
 250  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 251  */
 252 #ifdef CONFIG_CMD_JFFS2
 253 #       define CONFIG_JFFS2_DEV         "nor0"
 254 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x40000)
 255 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
 256 #endif
 257
 258 /*-----------------------------------------------------------------------
 259  * Cache Configuration
 260  */
 261 #define CONFIG_SYS_CACHELINE_SIZE       16
 262
 263 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 264                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 265 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 266                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 267 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 268 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 269                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 270                                          CF_ACR_EN | CF_ACR_SM_ALL)
 271 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 272                                          CF_CACR_DISD | CF_CACR_INVI | \
 273                                          CF_CACR_CEIB | CF_CACR_DCM | \
 274                                          CF_CACR_EUSP)
 275
 276 /*-----------------------------------------------------------------------
 277  * Memory bank definitions
 278  */
 279 /*
 280  * CS0 - NOR Flash
 281  * CS1 - Available
 282  * CS2 - Available
 283  * CS3 - Available
 284  * CS4 - Available
 285  * CS5 - Available
 286  */
 287
 288 #ifdef CONFIG_CF_SBF
 289 #define CONFIG_SYS_CS0_BASE             0x04000000
 290 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 291 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 292 #else
 293 #define CONFIG_SYS_CS0_BASE             0x00000000
 294 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 295 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 296 #endif
 297
 298 #endif                          /* _M52277EVB_H */