1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF52277 EVB board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
26 #undef CONFIG_WATCHDOG
28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
33 #define CONFIG_BOOTP_BOOTFILESIZE
35 #define CONFIG_HOSTNAME "M52277EVB"
36 #define CONFIG_SYS_UBOOT_END 0x3FFFF
37 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
38 #ifdef CONFIG_SYS_STMICRO_BOOT
39 /* ST Micro serial flash */
40 #define CONFIG_EXTRA_ENV_SETTINGS \
41 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
42 "loadaddr=0x40010000\0" \
43 "uboot=u-boot.bin\0" \
44 "load=loadb ${loadaddr} ${baudrate};" \
45 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
46 "upd=run load; run prog\0" \
47 "prog=sf probe 0:2 10000 1;" \
49 "sf write ${loadaddr} 0 30000;" \
53 #ifdef CONFIG_SYS_SPANSION_BOOT
54 #define CONFIG_EXTRA_ENV_SETTINGS \
55 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
56 "loadaddr=0x40010000\0" \
57 "uboot=u-boot.bin\0" \
58 "load=loadb ${loadaddr} ${baudrate}\0" \
59 "upd=run load; run prog\0" \
60 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
61 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
62 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
63 __stringify(CONFIG_SYS_UBOOT_END) ";" \
64 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
65 " ${filesize}; save\0" \
66 "updsbf=run loadsbf; run progsbf\0" \
67 "loadsbf=loadb ${loadaddr} ${baudrate};" \
68 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
69 "progsbf=sf probe 0:2 10000 1;" \
71 "sf write ${loadaddr} 0 30000;" \
77 #define CONFIG_SPLASH_SCREEN
78 #define CONFIG_LCD_LOGO
79 #define CONFIG_SHARP_LQ035Q7DH06
84 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
85 #define CONFIG_SYS_USB_EHCI_CPU_INIT
91 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
97 #define CONFIG_SYS_I2C
98 #define CONFIG_SYS_I2C_FSL
99 #define CONFIG_SYS_FSL_I2C_SPEED 80000
100 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
101 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
102 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
104 /* DSPI and Serial Flash */
105 #define CONFIG_CF_DSPI
106 #define CONFIG_SYS_SBFHDR_SIZE 0x7
108 /* Input, PCI, Flexbus, and VCO */
109 #define CONFIG_EXTRA_CLOCK
111 #define CONFIG_SYS_INPUT_CLKSRC 16000000
113 #define CONFIG_PRAM 2048 /* 2048 KB */
115 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
117 #define CONFIG_SYS_MBAR 0xFC000000
120 * Low Level Configuration Settings
121 * (address mappings, register initial values, etc.)
122 * You should know what you are doing if you make changes here.
126 * Definitions for initial stack pointer and data area (in DPRAM)
128 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
129 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
130 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
131 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
132 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
133 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
136 * Start addresses for the final memory configuration
137 * (Set up by the startup code)
138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
140 #define CONFIG_SYS_SDRAM_BASE 0x40000000
141 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
142 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
143 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
144 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
145 #define CONFIG_SYS_SDRAM_EMOD 0x81810000
146 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
147 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
150 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
152 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
154 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
155 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
156 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
158 /* Initial Memory map for Linux */
159 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
160 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
163 * Configuration for environment
164 * Environment is not embedded in u-boot. First time runing may have env
165 * crc error warning if there is no correct environment on the flash.
167 #define CONFIG_ENV_OVERWRITE 1
169 /*-----------------------------------------------------------------------
172 #ifdef CONFIG_SYS_STMICRO_BOOT
173 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
174 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
176 #ifdef CONFIG_SYS_SPANSION_BOOT
177 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
178 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
181 #ifdef CONFIG_SYS_FLASH_CFI
182 # define CONFIG_FLASH_SPANSION_S29WS_N 1
183 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
184 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
185 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
186 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
187 # define CONFIG_SYS_FLASH_CHECKSUM
188 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
191 #define LDS_BOARD_TEXT \
192 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
193 arch/m68k/lib/built-in.o (.text*)
196 * This is setting for JFFS2 support in u-boot.
197 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
199 #ifdef CONFIG_CMD_JFFS2
200 # define CONFIG_JFFS2_DEV "nor0"
201 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
202 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
205 /*-----------------------------------------------------------------------
206 * Cache Configuration
208 #define CONFIG_SYS_CACHELINE_SIZE 16
210 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
211 CONFIG_SYS_INIT_RAM_SIZE - 8)
212 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
213 CONFIG_SYS_INIT_RAM_SIZE - 4)
214 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
215 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
216 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
217 CF_ACR_EN | CF_ACR_SM_ALL)
218 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
219 CF_CACR_DISD | CF_CACR_INVI | \
220 CF_CACR_CEIB | CF_CACR_DCM | \
223 /*-----------------------------------------------------------------------
224 * Memory bank definitions
236 #define CONFIG_SYS_CS0_BASE 0x04000000
237 #define CONFIG_SYS_CS0_MASK 0x00FF0001
238 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
240 #define CONFIG_SYS_CS0_BASE 0x00000000
241 #define CONFIG_SYS_CS0_MASK 0x00FF0001
242 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
245 #endif /* _M52277EVB_H */