1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF52277 EVB board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT (0)
24 #undef CONFIG_WATCHDOG
26 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
31 #define CONFIG_BOOTP_BOOTFILESIZE
33 #define CONFIG_HOSTNAME "M52277EVB"
34 #define CONFIG_SYS_UBOOT_END 0x3FFFF
35 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
36 #ifdef CONFIG_SYS_STMICRO_BOOT
37 /* ST Micro serial flash */
38 #define CONFIG_EXTRA_ENV_SETTINGS \
39 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
40 "loadaddr=0x40010000\0" \
41 "uboot=u-boot.bin\0" \
42 "load=loadb ${loadaddr} ${baudrate};" \
43 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
44 "upd=run load; run prog\0" \
45 "prog=sf probe 0:2 10000 1;" \
47 "sf write ${loadaddr} 0 30000;" \
51 #ifdef CONFIG_SYS_SPANSION_BOOT
52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
54 "loadaddr=0x40010000\0" \
55 "uboot=u-boot.bin\0" \
56 "load=loadb ${loadaddr} ${baudrate}\0" \
57 "upd=run load; run prog\0" \
58 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
59 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
60 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
61 __stringify(CONFIG_SYS_UBOOT_END) ";" \
62 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
63 " ${filesize}; save\0" \
64 "updsbf=run loadsbf; run progsbf\0" \
65 "loadsbf=loadb ${loadaddr} ${baudrate};" \
66 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
67 "progsbf=sf probe 0:2 10000 1;" \
69 "sf write ${loadaddr} 0 30000;" \
75 #define CONFIG_SPLASH_SCREEN
76 #define CONFIG_LCD_LOGO
77 #define CONFIG_SHARP_LQ035Q7DH06
82 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
83 #define CONFIG_SYS_USB_EHCI_CPU_INIT
89 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
96 #define CONFIG_SYS_I2C
97 #define CONFIG_SYS_I2C_FSL
98 #define CONFIG_SYS_FSL_I2C_SPEED 80000
99 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
100 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
101 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
103 /* DSPI and Serial Flash */
104 #define CONFIG_CF_DSPI
105 #define CONFIG_SYS_SBFHDR_SIZE 0x7
106 #ifdef CONFIG_CMD_SPI
107 # define CONFIG_SYS_DSPI_CS2
109 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
110 DSPI_CTAR_PCSSCK_1CLK | \
111 DSPI_CTAR_PASC(0) | \
113 DSPI_CTAR_CSSCK(0) | \
118 /* Input, PCI, Flexbus, and VCO */
119 #define CONFIG_EXTRA_CLOCK
121 #define CONFIG_SYS_INPUT_CLKSRC 16000000
123 #define CONFIG_PRAM 2048 /* 2048 KB */
125 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
127 #define CONFIG_SYS_MBAR 0xFC000000
130 * Low Level Configuration Settings
131 * (address mappings, register initial values, etc.)
132 * You should know what you are doing if you make changes here.
136 * Definitions for initial stack pointer and data area (in DPRAM)
138 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
139 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
140 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
141 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
142 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
143 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
148 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
150 #define CONFIG_SYS_SDRAM_BASE 0x40000000
151 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
152 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
153 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
154 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
155 #define CONFIG_SYS_SDRAM_EMOD 0x81810000
156 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
157 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
159 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
160 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
163 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
165 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
168 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
169 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
171 /* Initial Memory map for Linux */
172 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
173 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
176 * Configuration for environment
177 * Environment is not embedded in u-boot. First time runing may have env
178 * crc error warning if there is no correct environment on the flash.
180 #define CONFIG_ENV_OVERWRITE 1
182 /*-----------------------------------------------------------------------
185 #ifdef CONFIG_SYS_STMICRO_BOOT
186 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
187 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
188 # define CONFIG_ENV_OFFSET 0x30000
189 # define CONFIG_ENV_SIZE 0x1000
190 # define CONFIG_ENV_SECT_SIZE 0x10000
192 #ifdef CONFIG_SYS_SPANSION_BOOT
193 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
194 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
195 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
196 # define CONFIG_ENV_SIZE 0x1000
197 # define CONFIG_ENV_SECT_SIZE 0x8000
200 #ifdef CONFIG_SYS_FLASH_CFI
201 # define CONFIG_FLASH_SPANSION_S29WS_N 1
202 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
203 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
204 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
205 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
206 # define CONFIG_SYS_FLASH_CHECKSUM
207 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
210 #define LDS_BOARD_TEXT \
211 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
212 arch/m68k/lib/built-in.o (.text*)
215 * This is setting for JFFS2 support in u-boot.
216 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
218 #ifdef CONFIG_CMD_JFFS2
219 # define CONFIG_JFFS2_DEV "nor0"
220 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
221 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
224 /*-----------------------------------------------------------------------
225 * Cache Configuration
227 #define CONFIG_SYS_CACHELINE_SIZE 16
229 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
230 CONFIG_SYS_INIT_RAM_SIZE - 8)
231 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
232 CONFIG_SYS_INIT_RAM_SIZE - 4)
233 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
234 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
235 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
236 CF_ACR_EN | CF_ACR_SM_ALL)
237 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
238 CF_CACR_DISD | CF_CACR_INVI | \
239 CF_CACR_CEIB | CF_CACR_DCM | \
242 /*-----------------------------------------------------------------------
243 * Memory bank definitions
255 #define CONFIG_SYS_CS0_BASE 0x04000000
256 #define CONFIG_SYS_CS0_MASK 0x00FF0001
257 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
259 #define CONFIG_SYS_CS0_BASE 0x00000000
260 #define CONFIG_SYS_CS0_MASK 0x00FF0001
261 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
264 #endif /* _M52277EVB_H */