include/configs/M5208EVBE.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5208EVBe.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 #ifndef _M5208EVBE_H
  10 #define _M5208EVBE_H
  11
  12 /*
  13  * High Level Configuration Options
  14  * (easy to change)
  15  */
  16 #define CONFIG_SYS_UART_PORT            (0)
  17
  18 #define CONFIG_WATCHDOG_TIMEOUT         5000
  19
  20 /* I2C */
  21
  22 #ifdef CONFIG_MCFFEC
  23 #       define CONFIG_IPADDR    192.162.1.2
  24 #       define CONFIG_NETMASK   255.255.255.0
  25 #       define CONFIG_SERVERIP  192.162.1.1
  26 #       define CONFIG_GATEWAYIP 192.162.1.1
  27 #endif                          /* CONFIG_MCFFEC */
  28
  29 #define CONFIG_HOSTNAME         "M5208EVBe"
  30 #define CONFIG_EXTRA_ENV_SETTINGS               \
  31         "netdev=eth0\0"                         \
  32         "loadaddr=40010000\0"                   \
  33         "u-boot=u-boot.bin\0"                   \
  34         "load=tftp ${loadaddr) ${u-boot}\0"     \
  35         "upd=run load; run prog\0"              \
  36         "prog=prot off 0 3ffff;"                \
  37         "era 0 3ffff;"                          \
  38         "cp.b ${loadaddr} 0 ${filesize};"       \
  39         "save\0"                                \
  40         ""
  41
  42 #define CONFIG_PRAM             512     /* 512 KB */
  43
  44 #define CONFIG_SYS_CLK          166666666       /* CPU Core Clock */
  45 #define CONFIG_SYS_PLL_ODR      0x36
  46 #define CONFIG_SYS_PLL_FDR      0x7D
  47
  48 #define CONFIG_SYS_MBAR         0xFC000000
  49
  50 /*
  51  * Low Level Configuration Settings
  52  * (address mappings, register initial values, etc.)
  53  * You should know what you are doing if you make changes here.
  54  */
  55 /* Definitions for initial stack pointer and data area (in DPRAM) */
  56 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  57 #define CONFIG_SYS_INIT_RAM_SIZE                0x4000  /* Size of used area in internal SRAM */
  58 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  59
  60 /*
  61  * Start addresses for the final memory configuration
  62  * (Set up by the startup code)
  63  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  64  */
  65 #define CFG_SYS_SDRAM_BASE              0x40000000
  66 #define CFG_SYS_SDRAM_SIZE              32      /* SDRAM size in MB */
  67 #define CFG_SYS_SDRAM_CFG1              0x43711630
  68 #define CFG_SYS_SDRAM_CFG2              0x56670000
  69 #define CFG_SYS_SDRAM_CTRL              0xE1002000
  70 #define CFG_SYS_SDRAM_EMOD              0x80010000
  71 #define CFG_SYS_SDRAM_MODE              0x00CD0000
  72
  73 /*
  74  * For booting Linux, the board info and command line data
  75  * have to be in the first 8 MB of memory, since this is
  76  * the maximum mapped by the Linux kernel during initialization ??
  77  */
  78 #define CONFIG_SYS_BOOTMAPSZ            (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  79
  80 /* FLASH organization */
  81 #ifdef CONFIG_SYS_FLASH_CFI
  82 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
  83 #endif
  84
  85 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  86
  87 /*
  88  * Configuration for environment
  89  * Environment is embedded in u-boot in the second sector of the flash
  90  */
  91
  92 #define LDS_BOARD_TEXT \
  93         . = DEFINED(env_offset) ? env_offset : .; \
  94         env/embedded.o(.text*);
  95
  96 /* Cache Configuration */
  97
  98 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  99                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 100 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 101                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 102 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 103 #define CONFIG_SYS_CACHE_ACR0           (CFG_SYS_SDRAM_BASE | \
 104                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 105                                          CF_ACR_EN | CF_ACR_SM_ALL)
 106 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 107                                          CF_CACR_DISD | CF_CACR_INVI | \
 108                                          CF_CACR_CEIB | CF_CACR_DCM | \
 109                                          CF_CACR_EUSP)
 110
 111 /* Chipselect bank definitions */
 112 /*
 113  * CS0 - NOR Flash
 114  * CS1 - Available
 115  * CS2 - Available
 116  * CS3 - Available
 117  * CS4 - Available
 118  * CS5 - Available
 119  */
 120 #define CONFIG_SYS_CS0_BASE             0
 121 #define CONFIG_SYS_CS0_MASK             0x007F0001
 122 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 123
 124 #endif                          /* _M5208EVBE_H */