1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5208EVBe.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * High Level Configuration Options
16 #define CONFIG_MCFUART
17 #define CONFIG_SYS_UART_PORT (0)
19 #undef CONFIG_WATCHDOG
20 #define CONFIG_WATCHDOG_TIMEOUT 5000
23 # define CONFIG_MII_INIT 1
24 # define CONFIG_SYS_DISCOVER_PHY
25 # define CONFIG_SYS_RX_ETH_BUFFER 8
26 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
27 # define CONFIG_HAS_ETH1
28 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
29 # ifndef CONFIG_SYS_DISCOVER_PHY
30 # define FECDUPLEX FULL
31 # define FECSPEED _100BASET
33 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
34 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
36 # endif /* CONFIG_SYS_DISCOVER_PHY */
43 #define CONFIG_SYS_I2C_FSL
44 #define CONFIG_SYS_FSL_I2C_SPEED 80000
45 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
46 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
47 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
49 #define CONFIG_UDP_CHECKSUM
52 # define CONFIG_IPADDR 192.162.1.2
53 # define CONFIG_NETMASK 255.255.255.0
54 # define CONFIG_SERVERIP 192.162.1.1
55 # define CONFIG_GATEWAYIP 192.162.1.1
56 #endif /* CONFIG_MCFFEC */
58 #define CONFIG_HOSTNAME "M5208EVBe"
59 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "loadaddr=40010000\0" \
62 "u-boot=u-boot.bin\0" \
63 "load=tftp ${loadaddr) ${u-boot}\0" \
64 "upd=run load; run prog\0" \
65 "prog=prot off 0 3ffff;" \
67 "cp.b ${loadaddr} 0 ${filesize};" \
71 #define CONFIG_PRAM 512 /* 512 KB */
73 #define CONFIG_SYS_LOAD_ADDR 0x40010000
75 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
76 #define CONFIG_SYS_PLL_ODR 0x36
77 #define CONFIG_SYS_PLL_FDR 0x7D
79 #define CONFIG_SYS_MBAR 0xFC000000
82 * Low Level Configuration Settings
83 * (address mappings, register initial values, etc.)
84 * You should know what you are doing if you make changes here.
86 /* Definitions for initial stack pointer and data area (in DPRAM) */
87 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
88 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
89 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
90 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
91 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
94 * Start addresses for the final memory configuration
95 * (Set up by the startup code)
96 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
98 #define CONFIG_SYS_SDRAM_BASE 0x40000000
99 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
100 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
101 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
102 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000
103 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
104 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
106 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
107 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
109 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
110 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
113 * For booting Linux, the board info and command line data
114 * have to be in the first 8 MB of memory, since this is
115 * the maximum mapped by the Linux kernel during initialization ??
117 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
118 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
120 /* FLASH organization */
121 #ifdef CONFIG_SYS_FLASH_CFI
122 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
123 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
124 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
125 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
128 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
131 * Configuration for environment
132 * Environment is embedded in u-boot in the second sector of the flash
135 #define LDS_BOARD_TEXT \
136 . = DEFINED(env_offset) ? env_offset : .; \
137 env/embedded.o(.text*);
139 /* Cache Configuration */
140 #define CONFIG_SYS_CACHELINE_SIZE 16
142 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
143 CONFIG_SYS_INIT_RAM_SIZE - 8)
144 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
145 CONFIG_SYS_INIT_RAM_SIZE - 4)
146 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
147 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
148 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
149 CF_ACR_EN | CF_ACR_SM_ALL)
150 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
151 CF_CACR_DISD | CF_CACR_INVI | \
152 CF_CACR_CEIB | CF_CACR_DCM | \
155 /* Chipselect bank definitions */
164 #define CONFIG_SYS_CS0_BASE 0
165 #define CONFIG_SYS_CS0_MASK 0x007F0001
166 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
168 #endif /* _M5208EVBE_H */