2 * Configuation settings for the Freescale MCF5208EVBe.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Configuration Options
17 #define CONFIG_MCFUART
18 #define CONFIG_SYS_UART_PORT (0)
20 #undef CONFIG_WATCHDOG
21 #define CONFIG_WATCHDOG_TIMEOUT 5000
26 # define CONFIG_MII_INIT 1
27 # define CONFIG_SYS_DISCOVER_PHY
28 # define CONFIG_SYS_RX_ETH_BUFFER 8
29 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
30 # define CONFIG_HAS_ETH1
32 # define CONFIG_SYS_FEC0_PINMUX 0
33 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
34 # define MCFFEC_TOUT_LOOP 50000
35 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
36 # ifndef CONFIG_SYS_DISCOVER_PHY
37 # define FECDUPLEX FULL
38 # define FECSPEED _100BASET
40 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 # endif /* CONFIG_SYS_DISCOVER_PHY */
51 #define CONFIG_SYS_I2C
52 #define CONFIG_SYS_I2C_FSL
53 #define CONFIG_SYS_FSL_I2C_SPEED 80000
54 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
55 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
56 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
58 #define CONFIG_UDP_CHECKSUM
61 # define CONFIG_IPADDR 192.162.1.2
62 # define CONFIG_NETMASK 255.255.255.0
63 # define CONFIG_SERVERIP 192.162.1.1
64 # define CONFIG_GATEWAYIP 192.162.1.1
65 #endif /* CONFIG_MCFFEC */
67 #define CONFIG_HOSTNAME M5208EVBe
68 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "loadaddr=40010000\0" \
71 "u-boot=u-boot.bin\0" \
72 "load=tftp ${loadaddr) ${u-boot}\0" \
73 "upd=run load; run prog\0" \
74 "prog=prot off 0 3ffff;" \
76 "cp.b ${loadaddr} 0 ${filesize};" \
80 #define CONFIG_PRAM 512 /* 512 KB */
81 #define CONFIG_SYS_LONGHELP /* undef to save memory */
83 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
84 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
85 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
86 #define CONFIG_SYS_LOAD_ADDR 0x40010000
88 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
89 #define CONFIG_SYS_PLL_ODR 0x36
90 #define CONFIG_SYS_PLL_FDR 0x7D
92 #define CONFIG_SYS_MBAR 0xFC000000
95 * Low Level Configuration Settings
96 * (address mappings, register initial values, etc.)
97 * You should know what you are doing if you make changes here.
99 /* Definitions for initial stack pointer and data area (in DPRAM) */
100 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
101 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
102 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
103 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
111 #define CONFIG_SYS_SDRAM_BASE 0x40000000
112 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
113 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
114 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
115 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000
116 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
117 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
119 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
120 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
122 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
123 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
125 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
126 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
129 * For booting Linux, the board info and command line data
130 * have to be in the first 8 MB of memory, since this is
131 * the maximum mapped by the Linux kernel during initialization ??
133 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
134 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
136 /* FLASH organization */
137 #define CONFIG_SYS_FLASH_CFI
138 #ifdef CONFIG_SYS_FLASH_CFI
139 # define CONFIG_FLASH_CFI_DRIVER 1
140 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
141 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
142 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
143 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
144 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
147 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
150 * Configuration for environment
151 * Environment is embedded in u-boot in the second sector of the flash
153 #define CONFIG_ENV_OFFSET 0x2000
154 #define CONFIG_ENV_SIZE 0x1000
155 #define CONFIG_ENV_SECT_SIZE 0x2000
157 #define LDS_BOARD_TEXT \
158 . = DEFINED(env_offset) ? env_offset : .; \
159 env/embedded.o(.text*);
161 /* Cache Configuration */
162 #define CONFIG_SYS_CACHELINE_SIZE 16
164 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
165 CONFIG_SYS_INIT_RAM_SIZE - 8)
166 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
167 CONFIG_SYS_INIT_RAM_SIZE - 4)
168 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
169 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
170 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
171 CF_ACR_EN | CF_ACR_SM_ALL)
172 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
173 CF_CACR_DISD | CF_CACR_INVI | \
174 CF_CACR_CEIB | CF_CACR_DCM | \
177 /* Chipselect bank definitions */
186 #define CONFIG_SYS_CS0_BASE 0
187 #define CONFIG_SYS_CS0_MASK 0x007F0001
188 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
190 #endif /* _M5208EVBE_H */